2 citations · 10 across the 11 of their papers we have counts for
9 papers · 1 filter
ChipMind: Retrieval-Augmented Reasoning for Long-Context Circuit Design Specifications
Changwen Xing, SamZaak Wong, Xinlai Wan +9
While Large Language Models (LLMs) demonstrate immense potential for automating integrated circuit (IC) development, their practical deployment is fundamentally limited by restrict…
VerilogMonkey: Exploring Parallel Scaling for Automated Verilog Code Generation with LLMs
Juxin Niu, Yuxin Du, Dan Niu +3
We present VerilogMonkey, an empirical study of parallel scaling for the under-explored task of automated Verilog generation. Parallel scaling improves LLM performance by sampling…
FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification
Gwok-Waa Wan, Shengchu Su, Ruihu Wang +15
Despite the transformative potential of Large Language Models (LLMs) in hardware design, a comprehensive evaluation of their capabilities in design verification remains underexplor…
ChatModel: Automating Reference Model Design and Verification with LLMs
Jianmin Ye, Tianyang Liu, Qi Tian +3
As the complexity of integrated circuit designs continues to escalate, functional verification becomes increasingly challenging. Reference models, critical for accelerating the ver…
ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflection
Juxin Niu, Xiangfeng Liu, Dan Niu +3
Coding with hardware description languages (HDLs) such as Verilog is a time-intensive and laborious task. With the rapid advancement of large language models (LLMs), there is incre…
VeriDebug: A Unified LLM for Verilog Debugging via Contrastive Embedding and Guided Correction
Ning Wang, Bingkun Yao, Jie Zhou +4
Large Language Models (LLMs) have demonstrated remarkable potential in debugging for various programming languages. However, the application of LLMs to Verilog debugging remains in…
Insights from Verification: Training a Verilog Generation LLM with Reinforcement Learning with Testbench Feedback
Ning Wang, Bingkun Yao, Jie Zhou +4
Large language models (LLMs) have shown strong performance in Verilog generation from natural language description. However, ensuring the functional correctness of the generated co…
From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verification
Junhao Ye, Yuchen Hu, Ke Xu +8
Verification presents a major bottleneck in Integrated Circuit (IC) development, consuming nearly 70% of the total development effort. While the Universal Verification Methodology…
Insights from Rights and Wrongs: A Large Language Model for Solving Assertion Failures in RTL Design
Jie Zhou, Youshu Ji, Ning Wang +7
SystemVerilog Assertions (SVAs) are essential for verifying Register Transfer Level (RTL) designs, as they can be embedded into key functional paths to detect unintended behaviours…