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cs.AR2024★ 2 cited
Location is Key: Leveraging Large Language Model for Functional Bug Localization in Verilog
Bingkun Yao, Ning Wang, Jie Zhou +4
Bug localization in Verilog code is a crucial and time-consuming task during the verification of hardware design. Since introduction, Large Language Models (LLMs) have showed their…
cs.AR2024★ 2 cited
Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learning
Ning Wang, Bingkun Yao, Jie Zhou +3
Recent advancements in large language models (LLMs) have sparked significant interest in the automatic generation of Register Transfer Level (RTL) designs, particularly using Veril…