2 citations · 13 across the 15 of their papers we have counts for
4 papers · 1 filter
SeqFeed: Improving Agentic RTL Code Generation with Sequential Behavior Feedback
Yuxin Du, Juxin Niu, Tao Hu +3
RTL code generation is a critical stage in hardware design, and the emergence of agentic systems offers new opportunities to automate this process. To generate correct RTL code, ag…
ZK-Tracer: A High-Performance Heterogeneous Accelerator for Zero-Knowledge VM Trace Generation
Jieran Cui, Zhengkai Wen, Haowen Fang +6
Zero-knowledge virtual machines (zkVMs) are a key technology for driving the large-scale adoption of zero-knowledge proofs (ZKP), but their performance bottlenecks severely limit t…
UVMarvel: an Automated LLM-aided UVM Machine for Subsystem-level RTL Verification
Junhao Ye, Dingrong Pan, Hanyuan Liu +7
Verification presents a major bottleneck in Integrated Circuit (IC) development, consuming nearly 70% of total effort. While the Universal Verification Methodology (UVM) improves r…
Automated SVA Generation with LLMs
Lik Tung Fu, Qihang Wang, Shaokai Ren +4
Functional verification remains a dominant cost in modern IC development, and SystemVerilog Assertions (SVAs) are critical for simulation-based monitoring and formal property check…