2 citations · 13 across the 15 of their papers we have counts for
4 papers · 1 filter
UVLLM: An Automated Universal RTL Verification Framework using LLMs
Yuchen Hu, Junhao Ye, Ke Xu +11
Verifying hardware designs in embedded systems is crucial but often labor-intensive and time-consuming. While existing solutions have improved automation, they frequently rely on u…
Location is Key: Leveraging Large Language Model for Functional Bug Localization in Verilog
Bingkun Yao, Ning Wang, Jie Zhou +4
Bug localization in Verilog code is a crucial and time-consuming task during the verification of hardware design. Since introduction, Large Language Models (LLMs) have showed their…
Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learning
Ning Wang, Bingkun Yao, Jie Zhou +3
Recent advancements in large language models (LLMs) have sparked significant interest in the automatic generation of Register Transfer Level (RTL) designs, particularly using Veril…
MEIC: Re-thinking RTL Debug Automation using LLMs
Ke Xu, Jialin Sun, Yuchen Hu +4
The deployment of Large Language Models (LLMs) for code debugging (e.g., C and Python) is widespread, benefiting from their ability to understand and interpret intricate concepts.…