26 citations · 32 across the 8 of their papers we have counts for
8 papers
Python in the front, party in the Backline: compiling quantum workloads across CPUs, GPUs, and FPGAs
Joseph K. L. Lee, Mehrdad Malekmohammadi, Hong-Sheng Zheng +10
Moving from quantum research and development to production-grade, fault-tolerant quantum workload execution remains one of the most significant challenges facing quantum platform b…
Pragma driven shared memory parallelism in Zig by supporting OpenMP loop directives
David Kacs, Joseph Lee, Justs Zarins +1
The Zig programming language, which is designed to provide performance and safety as first class concerns, has become popular in recent years. Given that Zig is built upon LLVM, an…
Implementing OpenMP for Zig to enable its use in HPC context
David Kacs, Nick Brown, Joseph Lee
This extended abstract explores supporting OpenMP in the Zig programming language. Whilst, C and Fortran are currently the main languages used to implement HPC applications, Zig pr…
Quantum Task Offloading with the OpenMP API
Joseph K. L. Lee, Oliver T. Brown, Mark Bull +4
Most of the widely used quantum programming languages and libraries are not designed for the tightly coupled nature of hybrid quantum-classical algorithms, which run on quantum res…
Is RISC-V ready for HPC prime-time: Evaluating the 64-core Sophon SG2042 RISC-V CPU
Nick Brown, Maurice Jamieson, Joseph Lee +1
The Sophon SG2042 is the world's first commodity 64-core RISC-V CPU for high performance workloads and an important question is whether the SG2042 has the potential to encourage th…
Experiences of running an HPC RISC-V testbed
Nick Brown, Maurice Jamieson, Joseph K. L. Lee
Funded by the UK ExCALIBUR H\&ES exascale programme, in early 2022 a RISC-V testbed for HPC was stood up to provide free access for scientific software developers to experiment wit…
Backporting RISC-V Vector assembly
Joseph K. L. Lee, Maurice Jamieson, Nick Brown
Leveraging vectorisation, the ability for a CPU to apply operations to multiple elements of data concurrently, is critical for high performance workloads. However, at the time of w…
Test-driving RISC-V Vector hardware for HPC
Joseph K. L. Lee, Maurice Jamieson, Nick Brown +1
Whilst the RISC-V Vector extension (RVV) has been ratified, at the time of writing both hardware implementations and open source software support are still limited for vectorisatio…