13 citations · 57 across the 75 of their papers we have counts for
57 papers · 1 filter
Understanding the Power Consumption of Modern High Bandwidth Memory: Experimental Analysis and Modeling Using Real HBM2 DRAM Chips
Ataberk Olgun, Spiros Galanopoulos, Andreas Kosmas Kakolyris +4
We perform the first comprehensive experimental characterization of power consumed by real HBM2 DRAM chips. Our extensive characterization yields 1) the empirical basis for develop…
Terracotta: Enabling the Adoption of New DRAM Techniques via a Flexible DRAM Interface and Memory Controller
Harsh Songara, Konstantinos Kanellopoulos, F. Nisa Bostancı +6
DRAM continues to limit the performance, energy efficiency, and robustness of modern systems. Many prior works propose DRAM techniques that support in-DRAM computation, improve mem…
PipeDRAM: A Data-Transposition-Free Processing-Using-DRAM Architecture with Hardware/Software Pipelining
Geraldo F. Oliveira, Ataberk Olgun, Ismail Emir Yüksel +6
Processing-using-DRAM (PUD) architectures exploit the analog operational properties of DRAM to perform bulk bitwise Boolean and arithmetic operations inside memory arrays by organi…
CertiFlash: A Formal Verification Framework for Flash Translation Layers in Computational Solid State Drives
Harshita Gupta, Mayank Kabra, Rakesh Nadig +10
Data-intensive applications move large amounts of data from storage to the compute unit, incurring significant data movement overhead. Storage-centric computing reduces this overhe…
FLINT: Efficiently Leveraging High Bandwidth Flash for Capacity-Scalable LLM Inference Acceleration
Geraldo F. Oliveira, Arash Tavakkol, Xiangyu Zhu +10
LLM inference is increasingly constrained by accelerator memory capacity rather than compute throughput. This constraint is especially acute in single-accelerator and small-node in…
Experimental Study on System-Level Performance Impact of Read Disturbance in Modern SSDs
Yonggon Park, Hyunuk Cho, Onur Mutlu +2
This work investigates the system-level performance impact of read disturbance in modern NAND flash-based SSDs, aiming to provide new insights that can help develop better storage…
Exploring High-Bandwidth Flash for Modern LLM Inference: Opportunities and Challenges
Dowon Son, Yonggon Park, Hyunuk Cho +5
This work investigates the potential benefits and technical challenges of using high-bandwidth flash (HBF) for large language model (LLM) inference. HBF has gained increasing atten…
Demystifying DRAM Read Disturbance: Bridging the Gap Between Experimental Characterization and Device-Level Modeling of RowHammer and RowPress Phenomena
Haocong Luo, Longda Zhou, Ataberk Olgun +5
DRAM read disturbance, like RowHammer and RowPress, is a critical robustness issue where accessing DRAM can cause unintended bitflips in other unaccessed DRAM locations. DRAM read…
Enabling Fast, Efficient, and Low-Cost Genomic and Metagenomic Analyses via Storage-Centric System Designs
Nika Mansouri Ghiasi, Onur Mutlu
Due to the challenges of analyzing and storing massive volumes of genomic and metagenomic sequence data, significant efforts have been made to accelerate (meta)genomic analyses and…
GRAINS: Storage-Aware Algorithm-Architecture Co-Design Enabling High-Performance and Low-Cost Graph-Based Genome Analysis
Nika Mansouri Ghiasi, Harun Mustafa, Talu Güloglu +8
Graph-based representations of genome sequences have emerged as a powerful approach for representing massive genomic databases in an expressive and efficient way. Despite their ben…
Clutch: High Performance Vector-Scalar Comparison using DRAM via Chunked Temporal Coding
Daichi Tokuda, Tatsuya Kubo, Ismail Emir Yuksel +8
Vector-scalar comparison is a fundamental computation primitive that compares each element in a vector against a single scalar value. It is widely used in various data-intensive wo…
Architecture for Health Initiative (Arch4Health): Computational Challenges in Health-Related Applications and the Role of Computer Architecture in Addressing Them
Nika Mansouri Ghiasi, Konstantina Koliogeorgi, Onur Mutlu
Recent biotechnological advances enable high-throughput, low-cost, and accurate biological data generation. This wealth of data enables unique opportunities for advancing healthcar…
DejaVu: Why You Should Write to Your DRAM Rows Twice, Carefully
Haocong Luo, İsmail Emir Yüksel, Ataberk Olgun +4
We provide the first experimental demonstration of DejaVu, a phenomenon where the data previously written to DRAM cells affects DRAM's vulnerability to read disturbance. Our experi…
Ramulator 2.1: A Composable Memory System Simulator for Modern DRAM Systems
Haocong Luo, F. Nisa Bostancı, Ataberk Olgun +4
Ramulator 2.1 is a major overhaul of Ramulator 2.0 that substantially improves the simulator in three directions: 1) support of modern and emerging DRAM and memory-controller featu…
PuDGhost: Experimental Analysis of Computation Result Corruption in Processing-using-DRAM Operations on Real DRAM Chips and Implications for Future Systems
Daichi Tokuda, İsmail Emir Yüksel, Tatsuya Kubo +7
Processing-using-DRAM (PuD) is a promising computation paradigm that alleviates frequent data movement between main memory and processing units by using each DRAM column as a compu…
In-DRAM Signature Generation Using Simultaneous Multiple-Row Activation: An Experimental Study of Off-The-Shelf DRAM Chips
Umut Baser, Ismail Emir Yuksel, F. Nisa Bostanci +7
We experimentally demonstrate that it is possible to generate unique, repeatable, and device-specific signatures suitable for use as Physical Unclonable Function (PUF) responses in…
A Modern Large-Scale Memory Characterization Laboratory
Ataberk Olgun, Haocong Luo, Ismail Emir Yuksel +3
Real memory chip characterization yields insights into fundamental operational characteristics of modern memory, enabling new mechanisms that improve memory performance, robustness…
Machine Learning-Driven Intelligent Memory System Design: From On-Chip Caches to Storage
Rahul Bera, Rakesh Nadig, Onur Mutlu
Despite the data-rich environment in which memory systems of modern computing platforms operate, many state-of-the-art architectural policies employed in the memory system rely on…
DiscoRD: An Experimental Methodology for Quickly Discovering the Reliable Read Disturbance Threshold of Real DRAM Chips
Ataberk Olgun, F. Nisa Bostanci, Ismail Emir Yuksel +4
State-of-the-art DRAM read disturbance mitigations rely on the read disturbance threshold (RDT) (e.g., the number of aggressor row activations needed to induce the first read distu…
GenPairX: A Hardware-Algorithm Co-Designed Accelerator for Paired-End Read Mapping
Julien Eudine, Chu Li, Zhuo Cheng +11
Genome sequencing has become a central focus in computational biology. A genome study typically begins with sequencing, which produces millions to billions of short DNA fragments k…
Conduit: Programmer-Transparent Near-Data Processing Using Multiple Compute-Capable Resources in Solid State Drives
Rakesh Nadig, Vamanan Arulchelvan, Mayank Kabra +9
Solid-state drives (SSDs) are well suited for near-data processing (NDP) because they: (1) store large application datasets, and (2) support three NDP paradigms: in-storage process…
Athena: Synergizing Data Prefetching and Off-Chip Prediction via Online Reinforcement Learning
Rahul Bera, Zhenrong Lang, Caroline Hengartner +4
Prefetching and off-chip prediction are two techniques proposed to hide long memory access latencies in high-performance processors. In this work, we demonstrate that: (1) prefetch…
DCC: Data-Centric Compilation of Machine Learning Kernels for Processing-In-Memory Architectures
Peiming Yang, Sankeerth Durvasula, Ivan Fernandez +4
High-performance Host processors can integrate Processing-In-Memory (PIM) devices, which can accelerate memory-intensive kernels of Machine Learning (ML) models, including Large La…
In-DRAM True Random Number Generation Using Simultaneous Multiple-Row Activation: An Experimental Study of Real DRAM Chips
Ismail Emir Yuksel, Ataberk Olgun, F. Nisa Bostanci +5
In this work, we experimentally demonstrate that it is possible to generate true random numbers at high throughput and low latency in commercial off-the-shelf (COTS) DRAM chips by…