9 citations · 17 across the 3 of their papers we have counts for
3 papers
EPAC: The Last Dance
Filippo Mantovani, Fabio Banchelli, Pablo Vizcaino +36
This paper presents EPAC, a RISC-V-based accelerator chip developed within the European Processor Initiative (EPI) as part of a multi-year, multi-partner effort to build a European…
Exploiting long vectors with a CFD code: a co-design show case
Marc Blancafort, Roger Ferrer, Guillaume Houzeaux +2
A current trend in HPC systems is the utilization of architectures with SIMD or vector extensions to exploit data parallelism. There are several ways to take advantage of such mode…
Software Development Vehicles to enable extended and early co-design: a RISC-V and HPC case of study
Filippo Mantovani, Pablo Vizcaino, Fabio Banchelli +6
Prototyping HPC systems with low-to-mid technology readiness level (TRL) systems is critical for providing feedback to hardware designers, the system software team (e.g., compiler…