9 citations · 11 across the 3 of their papers we have counts for
3 papers
EPAC: The Last Dance
Filippo Mantovani, Fabio Banchelli, Pablo Vizcaino +36
This paper presents EPAC, a RISC-V-based accelerator chip developed within the European Processor Initiative (EPI) as part of a multi-year, multi-partner effort to build a European…
Exploiting long vectors with a CFD code: a co-design show case
Marc Blancafort, Roger Ferrer, Guillaume Houzeaux +2
A current trend in HPC systems is the utilization of architectures with SIMD or vector extensions to exploit data parallelism. There are several ways to take advantage of such mode…
RAVE: RISC-V Analyzer of Vector Executions, a QEMU tracing plugin
Pablo Vizcaino, Filippo Mantovani, Jesus Labarta +1
Simulators are crucial during the development of a chip, like the RISC-V accelerator designed in the European Processor Initiative project. In this paper, we showcase the limitatio…