14 citations · 32 across the 14 of their papers we have counts for
9 papers · 1 filter
X-HEEP: An Open-Source, Configurable and Extendible RISC-V Platform for TinyAI Applications
Simone Machetti, Pasquale Davide Schiavone, Giovanni Ansaloni +2
In this work, we present X-HEEP, an open-source, configurable, and extendible RISC-V platform for ultra-low-power edge applications (TinyAI). X-HEEP features the eXtendible Acceler…
Physical Design Exploration of a Wire-Friendly Domain-Specific Processor for Angstrom-Era Nodes
Lorenzo Ruotolo, Lara Orlandic, Pengbo Yu +8
This paper presents the physical design exploration of a domain-specific processor (DSIP) architecture targeted at machine learning (ML), addressing the challenges of interconnect…
e-GPU: An Open-Source and Configurable RISC-V Graphic Processing Unit for TinyAI Applications
Simone Machetti, Pasquale Davide Schiavone, Lara Orlandic +4
Graphics processing units (GPUs) excel at parallel processing, but remain largely unexplored in ultra-low-power edge devices (TinyAI) due to their power and area limitations, as we…
A flexible framework for early power and timing comparison of time-multiplexed CGRA kernel executions
Maxime Henri Aspros, Juan Sapriza, Giovanni Ansaloni +1
At the intersection between traditional CPU architectures and more specialized options such as FPGAs or ASICs lies the family of reconfigurable hardware architectures, termed Coars…
Systolic Arrays and Structured Pruning Co-design for Efficient Transformers in Edge Systems
Pedro Palacios, Rafael Medina, Jean-Luc Rouas +2
Efficient deployment of resource-intensive transformers on edge devices necessitates cross-stack optimization. We thus study the interrelation between structured pruning and systol…
Accelerator-driven Data Arrangement to Minimize Transformers Run-time on Multi-core Architectures
Alireza Amirshahi, Giovanni Ansaloni, David Atienza
The increasing complexity of transformer models in artificial intelligence expands their computational costs, memory usage, and energy consumption. Hardware acceleration tackles th…
A Soft SIMD Based Energy Efficient Computing Microarchitecture
Pengbo Yu, Alexandre Levisse, Mohit Gupta +4
The ever-increasing size and computational complexity of today's machine-learning algorithms pose an increasing strain on the underlying hardware. In this light, novel and dedicate…
Bit-Line Computing for CNN Accelerators Co-Design in Edge AI Inference
Marco Rios, Flavio Ponzina, Alexandre Levisse +2
By supporting the access of multiple memory words at the same time, Bit-line Computing (BC) architectures allow the parallel execution of bit-wise operations in-memory. At the arra…
ALPINE: Analog In-Memory Acceleration with Tight Processor Integration for Deep Learning
Joshua Klein, Irem Boybat, Yasir Qureshi +6
Analog in-memory computing (AIMC) cores offers significant performance and energy benefits for neural network inference with respect to digital logic (e.g., CPUs). AIMCs accelerate…