activity
20222025
most citedALPINE: Analog In-Memory Acceleration with Tight Processor Integration for Deep Learning

14 citations · 32 across the 14 of their papers we have counts for

collaborators

14 papers

cs.LG2025

Personalization on a Budget: Minimally-Labeled Continual Learning for Resource-Efficient Seizure Detection

Amirhossein Shahbazinia, Jonathan Dan, Jose A. Miranda +2

Objective: Epilepsy, a prevalent neurological disease, demands careful diagnosis and continuous care. Seizure detection remains challenging, as current clinical practice relies on…

cs.AR2025

X-HEEP: An Open-Source, Configurable and Extendible RISC-V Platform for TinyAI Applications

Simone Machetti, Pasquale Davide Schiavone, Giovanni Ansaloni +2

In this work, we present X-HEEP, an open-source, configurable, and extendible RISC-V platform for ultra-low-power edge applications (TinyAI). X-HEEP features the eXtendible Acceler…

cs.AR2025

Physical Design Exploration of a Wire-Friendly Domain-Specific Processor for Angstrom-Era Nodes

Lorenzo Ruotolo, Lara Orlandic, Pengbo Yu +8

This paper presents the physical design exploration of a domain-specific processor (DSIP) architecture targeted at machine learning (ML), addressing the challenges of interconnect…

cs.AR2025

e-GPU: An Open-Source and Configurable RISC-V Graphic Processing Unit for TinyAI Applications

Simone Machetti, Pasquale Davide Schiavone, Lara Orlandic +4

Graphics processing units (GPUs) excel at parallel processing, but remain largely unexplored in ultra-low-power edge devices (TinyAI) due to their power and area limitations, as we…

cs.AR2025★ 2 cited

A flexible framework for early power and timing comparison of time-multiplexed CGRA kernel executions

Maxime Henri Aspros, Juan Sapriza, Giovanni Ansaloni +1

At the intersection between traditional CPU architectures and more specialized options such as FPGAs or ASICs lies the family of reconfigurable hardware architectures, termed Coars…

eess.SP2025★ 1 cited

Mathematical model of parameters relevance in adaptive level-crossing sampling for electrocardiogram signals

Silvio Zanoli, Giovanni Ansaloni, Tomás Teijeiro +1

Digital acquisition of bio-signals has been mostly dominated by uniform time sampling following the Nyquist theorem. However, in recent years, new approaches have emerged, focused…

cs.AR2024★ 3 cited

Systolic Arrays and Structured Pruning Co-design for Efficient Transformers in Edge Systems

Pedro Palacios, Rafael Medina, Jean-Luc Rouas +2

Efficient deployment of resource-intensive transformers on edge devices necessitates cross-stack optimization. We thus study the interrelation between structured pruning and systol…

cs.LG2024★ 1 cited

MetaWearS: A Shortcut in Wearable Systems Lifecycle with Only a Few Shots

Alireza Amirshahi, Maedeh H. Toosi, Siamak Mohammadi +5

Wearable systems provide continuous health monitoring and can lead to early detection of potential health issues. However, the lifecycle of wearable systems faces several challenge…

cs.ET2024★ 9 cited

LionHeart: A Layer-based Mapping Framework for Heterogeneous Systems with Analog In-Memory Computing Tiles

Corey Lammie, Yuxuan Wang, Flavio Ponzina +7

When arranged in a crossbar configuration, resistive memory devices can be used to execute Matrix-Vector Multiplications (MVMs), the most dominant operation of many Machine Learnin…

cs.AR2023

Accelerator-driven Data Arrangement to Minimize Transformers Run-time on Multi-core Architectures

Alireza Amirshahi, Giovanni Ansaloni, David Atienza

The increasing complexity of transformer models in artificial intelligence expands their computational costs, memory usage, and energy consumption. Hardware acceleration tackles th…

cs.AR2022

A Soft SIMD Based Energy Efficient Computing Microarchitecture

Pengbo Yu, Alexandre Levisse, Mohit Gupta +4

The ever-increasing size and computational complexity of today's machine-learning algorithms pose an increasing strain on the underlying hardware. In this light, novel and dedicate…

cs.AR2022★ 2 cited

Bit-Line Computing for CNN Accelerators Co-Design in Edge AI Inference

Marco Rios, Flavio Ponzina, Alexandre Levisse +2

By supporting the access of multiple memory words at the same time, Bit-line Computing (BC) architectures allow the parallel execution of bit-wise operations in-memory. At the arra…

eess.SP2022

Event-based sampled ECG morphology reconstruction through self-similarity

Silvio Zanoli, Tomas Teijeiro, Giovanni Ansaloni +1

Background and Objective: Event-based analog-to-digital converters allow for sparse bio-signal acquisition, enabling local sub-Nyquist sampling frequency. However, aggressive event…

cs.AR2022★ 14 cited

ALPINE: Analog In-Memory Acceleration with Tight Processor Integration for Deep Learning

Joshua Klein, Irem Boybat, Yasir Qureshi +6

Analog in-memory computing (AIMC) cores offers significant performance and energy benefits for neural network inference with respect to digital logic (e.g., CPUs). AIMCs accelerate…