11 citations · 30 across the 8 of their papers we have counts for
8 papers
Efficient Real-Time Selective Genome Sequencing on Resource-Constrained Devices
Po Jui Shih, Hassaan Saadat, Sri Parameswaran +1
Third-generation nanopore sequencers offer a feature called selective sequencing or 'Read Until' that allows genomic reads to be analyzed in real-time and abandoned halfway, if not…
ApproxTrain: Fast Simulation of Approximate Multipliers for DNN Training and Inference
Jing Gong, Hassaan Saadat, Hasindu Gamaarachchi +3
Edge training of Deep Neural Networks (DNNs) is a desirable goal for continuous learning; however, it is hindered by the enormous computational power required by training. Hardware…
Fast Selective Flushing to Mitigate Contention-based Cache Timing Attacks
Tuo Li, Sri Parameswaran
Caches are widely used to improve performance in modern processors. By carefully evicting cache lines and identifying cache hit/miss time, contention-based cache timing channel att…
SIMF: Single-Instruction Multiple-Flush Mechanism for Processor Temporal Isolation
Tuo Li, Bradley Hopkins, Sri Parameswaran
Microarchitectural timing attacks are a type of information leakage attack, which exploit the time-shared microarchitectural components, such as caches, translation look-aside buff…
SecureD: A Secure Dual Core Embedded Processor
Roshan G. Ragel, Jude A. Ambrose, Sri Parameswaran
Security of embedded computing systems is becoming of paramount concern as these devices become more ubiquitous, contain personal information and are increasingly used for financia…
CIPARSim: Cache Intersection Property Assisted Rapid Single-pass FIFO Cache Simulation Technique
Mohammad Shihabul Haque, Jorgen Peddersen, Sri Parameswaran
In this paper, for the first time, we introduce a cache property called the Intersection Property that helps to reduce singlepass simulation time in a manner similar to inclusion p…
DEW: A Fast Level 1 Cache Simulation Approach for Embedded Processors with FIFO Replacement Policy
Mohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya +1
Increasing the speed of cache simulation to obtain hit/miss rates en- ables performance estimation, cache exploration for embedded sys- tems and energy estimation. Previously, such…
Previous Messages Provide the Key to Achieve Shannon Capacity in a Wiretap Channel
Shahid Mehraj Shah, Parameswaran S, Vinod Sharma
We consider a wiretap channel and use previously transmitted messages to generate a secret key which increases the secrecy capacity. This can be bootstrapped to increase the secrec…