6 papers
Theory-Level Autoformalization: From Isolated Statements to Unified Formal Knowledge Bases
Marcus J. Min, Mike He, Zhaoyu Li +5
Autoformalization translates informal natural language into formal, machine-verifiable languages. While most work focuses on individual statements, real formalization efforts are i…
SecIC3: Customizing IC3 for Hardware Security Verification
Qinhan Tan, Akash Gaonkar, Yu-Wei Fan +2
Recent years have seen significant advances in using formal verification to check hardware security properties. Of particular practical interest are checking confidentiality and in…
FLAG: Formal and LLM-assisted SVA Generation for Formal Specifications of On-Chip Communication Protocols
Yu-An Shih, Annie Lin, Aarti Gupta +1
Formal specifications of on-chip communication protocols are crucial for system-on-chip (SoC) design and verification. However, manually constructing these formal specifications fr…
Combined Scheduling, Memory Allocation and Tensor Replacement for Minimizing Off-Chip Data Accesses of DNN Accelerators
Yi Li, Aarti Gupta, Sharad Malik
Specialized hardware accelerators have been extensively used for Deep Neural Networks (DNNs) to provide power/performance benefits. These accelerators contain specialized hardware…
High-Level Synthesis for Packet-Processing Pipelines
Xiangyu Gao, Divya Raghunathan, Ruijie Fang +5
Compiling high-level programs to target high-speed packet-processing pipelines is a challenging combinatorial optimization problem. The compiler must configure the pipeline's resou…
Application-Level Validation of Accelerator Designs Using a Formal Software/Hardware Interface
Bo-Yuan Huang, Steven Lyubomirsky, Yi Li +10
Ideally, accelerator development should be as easy as software development. Several recent design languages/tools are working toward this goal, but actually testing early designs o…