48 citations · 86 across the 8 of their papers we have counts for
8 papers
CB-VER: A Stable Foundation for Modular Control Plane Verification
Dexin Zhang, Timothy Alberdingk Thijm, David Walker +1
Network operators are often interested in verifying \emph{eventually-stable properties} of network control planes: properties of control plane states that hold eventually, and hold…
ACORN: Network Control Plane Abstraction using Route Nondeterminism
Divya Raghunathan, Ryan Beckett, Aarti Gupta +1
Networks are hard to configure correctly, and misconfigurations occur frequently, leading to outages or security breaches. Formal verification techniques have been applied to guara…
Modular Control Plane Verification via Temporal Invariants
Timothy Alberdingk Thijm, Ryan Beckett, Aarti Gupta +1
Monolithic control plane verification cannot scale to hyperscale network architectures with tens of thousands of nodes, heterogeneous network policies and thousands of network chan…
Kirigami, the Verifiable Art of Network Cutting
Tim Alberdingk Thijm, Ryan Beckett, Aarti Gupta +1
We introduce a modular verification approach to network control plane verification, where we cut a network into smaller fragments to improve the scalability of SMT solving. Users p…
Control Plane Compression
Ryan Beckett, Aarti Gupta, Ratul Mahajan +1
We develop an algorithm capable of compressing large networks into a smaller ones with similar control plane behavior: For every stable routing solution in the large, original netw…
Instruction-Level Abstraction (ILA): A Uniform Specification for System-on-Chip (SoC) Verification
Bo-Yuan Huang, Hongce Zhang, Pramod Subramanyan +3
Modern Systems-on-Chip (SoC) designs are increasingly heterogeneous and contain specialized semi-programmable accelerators in addition to programmable processors. In contrast to th…
RTL2RTL Formal Equivalence: Boosting the Design Confidence
M V Achutha Kiran Kumar, Aarti Gupta, S S Bindumadhava
Increasing design complexity driven by feature and performance requirements and the Time to Market (TTM) constraints force a faster design and validation closure. This in turn enfo…
Verification of Embedded Memory Systems using Efficient Memory Modeling
Malay K. Ganai, Aarti Gupta, Pranav Ashar
We describe verification techniques for embedded memory systems using efficient memory modeling (EMM), without explicitly modeling each memory bit. We extend our previously propose…