3 citations · 9 across the 20 of their papers we have counts for
25 papers
Understanding the Power Consumption of Modern High Bandwidth Memory: Experimental Analysis and Modeling Using Real HBM2 DRAM Chips
Ataberk Olgun, Spiros Galanopoulos, Andreas Kosmas Kakolyris +4
We perform the first comprehensive experimental characterization of power consumed by real HBM2 DRAM chips. Our extensive characterization yields 1) the empirical basis for develop…
MORDOR: Mitigating Overheads of Read Disturbance Preventive Operations via Elastic Refresh Scheduling
Maria Makeenkova, Ataberk Olgun, F. Nisa Bostancı +3
Modern DRAM chips are susceptible to read disturbance phenomena such as RowHammer, where repeatedly accessing (hammering) a row of DRAM cells (i.e., a DRAM row) induces bitflips in…
Terracotta: Enabling the Adoption of New DRAM Techniques via a Flexible DRAM Interface and Memory Controller
Harsh Songara, Konstantinos Kanellopoulos, F. Nisa Bostancı +6
DRAM continues to limit the performance, energy efficiency, and robustness of modern systems. Many prior works propose DRAM techniques that support in-DRAM computation, improve mem…
PipeDRAM: A Data-Transposition-Free Processing-Using-DRAM Architecture with Hardware/Software Pipelining
Geraldo F. Oliveira, Ataberk Olgun, Ismail Emir Yüksel +6
Processing-using-DRAM (PUD) architectures exploit the analog operational properties of DRAM to perform bulk bitwise Boolean and arithmetic operations inside memory arrays by organi…
CertiFlash: A Formal Verification Framework for Flash Translation Layers in Computational Solid State Drives
Harshita Gupta, Mayank Kabra, Rakesh Nadig +10
Data-intensive applications move large amounts of data from storage to the compute unit, incurring significant data movement overhead. Storage-centric computing reduces this overhe…
ColumnKeeper: Efficient Solutions to the ColumnDisturb Vulnerability in DRAM-based Systems
Andreas Kosmas Kakolyris, F. Nisa Bostanci, Ataberk Olgun +7
Modern DRAM chips are vulnerable to read disturbance phenomena such as RowHammer and RowPress, which induce bitflips after accessing nearby rows a certain number of times (the read…
Ramulator 2.1: A Composable Memory System Simulator for Modern DRAM Systems
Haocong Luo, F. Nisa Bostancı, Ataberk Olgun +4
Ramulator 2.1 is a major overhaul of Ramulator 2.0 that substantially improves the simulator in three directions: 1) support of modern and emerging DRAM and memory-controller featu…
Memory-Centric Computing: Security Benefits and Challenges of Processing-in-DRAM
Ismail Emir Yuksel, F. Nisa Bostanci, Ataberk Olgun +1
Today's computing systems are processor-centric: they require frequent data movement between processing elements (e.g., CPU) and main memory (DRAM), leading to significant ineffici…
In-DRAM Signature Generation Using Simultaneous Multiple-Row Activation: An Experimental Study of Off-The-Shelf DRAM Chips
Umut Baser, Ismail Emir Yuksel, F. Nisa Bostanci +7
We experimentally demonstrate that it is possible to generate unique, repeatable, and device-specific signatures suitable for use as Physical Unclonable Function (PUF) responses in…
A Modern Large-Scale Memory Characterization Laboratory
Ataberk Olgun, Haocong Luo, Ismail Emir Yuksel +3
Real memory chip characterization yields insights into fundamental operational characteristics of modern memory, enabling new mechanisms that improve memory performance, robustness…
ScaleDisturb: Exploiting Temporal Asymmetry to Amplify Read Disturbance in Modern DRAM Chips
Jikun Wang, Haocong Luo, Ataberk Olgun +6
DRAM suffers from read disturbance phenomena (e.g., RowHammer and RowPress), where repeatedly accessing or continuously keeping open a DRAM row (aggressor row) induces bitflips in…
DiscoRD: An Experimental Methodology for Quickly Discovering the Reliable Read Disturbance Threshold of Real DRAM Chips
Ataberk Olgun, F. Nisa Bostanci, Ismail Emir Yuksel +4
State-of-the-art DRAM read disturbance mitigations rely on the read disturbance threshold (RDT) (e.g., the number of aggressor row activations needed to induce the first read distu…
In-DRAM True Random Number Generation Using Simultaneous Multiple-Row Activation: An Experimental Study of Real DRAM Chips
Ismail Emir Yuksel, Ataberk Olgun, F. Nisa Bostanci +5
In this work, we experimentally demonstrate that it is possible to generate true random numbers at high throughput and low latency in commercial off-the-shelf (COTS) DRAM chips by…
Cleaning up the Mess: Re-Evaluating the Real-System Modeling Accuracy of Ramulator 2.0
F. Nisa Bostanci, Haocong Luo, Ataberk Olgun +4
A MICRO 2024 best paper runner-up publication (the Mess paper) with all three artifact badges awarded (including ``Reproducible'') proposes a new benchmark to evaluate real and sim…
Understanding and Mitigating Covert Channel and Side Channel Vulnerabilities Introduced by RowHammer Defenses
F. Nisa Bostancı, Oğuzhan Canpolat, Ataberk Olgun +5
DRAM chips are vulnerable to read disturbance phenomena (e.g., RowHammer and RowPress), where repeatedly accessing or keeping open a DRAM row causes bitflips in nearby rows. Attack…
Variable Read Disturbance: An Experimental Analysis of Temporal Variation in DRAM Read Disturbance
Ataberk Olgun, F. Nisa Bostanci, Ismail Emir Yuksel +6
Modern DRAM chips are subject to read disturbance errors. State-of-the-art read disturbance mitigations rely on accurate and exhaustive characterization of the read disturbance thr…
Simultaneous Many-Row Activation in Off-the-Shelf DRAM Chips: Experimental Characterization and Analysis
Ismail Emir Yuksel, Yahya Can Tugrul, F. Nisa Bostanci +8
We experimentally analyze the computational capability of commercial off-the-shelf (COTS) DRAM chips and the robustness of these capabilities under various timing delays between DR…
Revisiting Main Memory-Based Covert and Side Channel Attacks in the Context of Processing-in-Memory
F. Nisa Bostanci, Konstantinos Kanellopoulos, Ataberk Olgun +6
We introduce IMPACT, a set of high-throughput main memory-based timing attacks that leverage characteristics of processing-in-memory (PiM) architectures to establish covert and sid…
MIMDRAM: An End-to-End Processing-Using-DRAM System for High-Throughput, Energy-Efficient and Programmer-Transparent Multiple-Instruction Multiple-Data Processing
Geraldo F. Oliveira, Ataberk Olgun, Abdullah Giray Yağlıkçı +4
Processing-using-DRAM (PUD) is a processing-in-memory (PIM) approach that uses a DRAM array's massive internal parallelism to execute very-wide data-parallel operations, in a singl…
Virtuoso: Enabling Fast and Accurate Virtual Memory Research via an Imitation-based Operating System Simulation Methodology
Konstantinos Kanellopoulos, Konstantinos Sgouras, F. Nisa Bostanci +7
The unprecedented growth in data demand from emerging applications has turned virtual memory (VM) into a major performance bottleneck. Researchers explore new hardware/OS co-design…
CoMeT: Count-Min-Sketch-based Row Tracking to Mitigate RowHammer at Low Cost
F. Nisa Bostanci, Ismail Emir Yuksel, Ataberk Olgun +5
We propose a new RowHammer mitigation mechanism, CoMeT, that prevents RowHammer bitflips with low area, performance, and energy costs in DRAM-based systems at very low RowHammer th…
Functionally-Complete Boolean Logic in Real DRAM Chips: Experimental Characterization and Analysis
Ismail Emir Yuksel, Yahya Can Tugrul, Ataberk Olgun +7
Processing-using-DRAM (PuD) is an emerging paradigm that leverages the analog operational properties of DRAM circuitry to enable massively parallel in-DRAM computation. PuD has the…
PULSAR: Simultaneous Many-Row Activation for Reliable and High-Performance Computing in Off-the-Shelf DRAM Chips
Ismail Emir Yuksel, Yahya Can Tugrul, F. Nisa Bostanci +8
Data movement between the processor and the main memory is a first-order obstacle against improving performance and energy efficiency in modern systems. To address this obstacle, P…
Ramulator 2.0: A Modern, Modular, and Extensible DRAM Simulator
Haocong Luo, Yahya Can Tuğrul, F. Nisa Bostancı +3
We present Ramulator 2.0, a highly modular and extensible DRAM simulator that enables rapid and agile implementation and evaluation of design changes in the memory controller and D…