4 papers
An Irredundant and Compressed Data Layout to Optimize Bandwidth Utilization of FPGA Accelerators
Corentin Ferry, Nicolas Derumigny, Steven Derrien +1
Memory bandwidth is known to be a performance bottleneck for FPGA accelerators, especially when they deal with large multi-dimensional data-sets. A large body of work focuses on re…
An Irredundant Decomposition of Data Flow with Affine Dependences
Corentin Ferry, Steven Derrien, Sanjay Rajopadhye
Optimization pipelines targeting polyhedral programs try to maximize the compute throughput. Traditional approaches favor reuse and temporal locality; while the communicated volume…
Maximal Atomic irRedundant Sets: a Usage-based Dataflow Partitioning Algorithm
Corentin Ferry, Steven Derrien, Sanjay Rajopadhye
Programs admitting a polyhedral representation can be transformed in many ways for locality and parallelism, notably loop tiling. Data flow analysis can then compute dependence rel…
Increasing FPGA Accelerators Memory Bandwidth with a Burst-Friendly Memory Layout
Corentin Ferry, Tomofumi Yuki, Steven Derrien +1
Offloading compute-intensive kernels to hardware accelerators relies on the large degree of parallelism offered by these platforms. However, the effective bandwidth of the memory i…