9 papers · 1 filter
Inter-Set Correlation-Aware Replacement Policy for Energy Efficient RTM-based Caches
Elham Cheshmikhani, Hamed Farbeh
Today's data-centric applications demand cache architectures that can scale with growing workloads while maintaining high performance and energy efficiency. Fundamental issues such…
ROBIN: Incremental Oblique Interleaved ECC for Reliability Improvement in STT-MRAM Caches
Elham Cheshmikhani, Hamed Farbeh, Hossein Asadi
Spin-Transfer Torque Magnetic RAM} (STT-MRAM) is a promising alternative for SRAMs in on-chip cache memories. Besides all its advantages, high error rate in STT-MRAM is a major lim…
Enhancing Reliability of STT-MRAM Caches by Eliminating Read Disturbance Accumulation
Elham Cheshmikhani, Hamed Farbeh, Hossein Asadi
Spin-Transfer Torque Magnetic RAM (STT-MRAM) as one of the most promising replacements for SRAMs in on-chip cache memories benefits from higher density and scalability, near-zero l…
An Analytical and Empirical Investigation of Tag Partitioning for Energy-Efficient Reliable Cache
Elham Cheshmikhani, Hamed Farbeh
Associative cache memory significantly influences processor performance and energy consumption. Because it occupies over half of the chip area, cache memory is highly susceptible t…
3RSeT: Read Disturbance Rate Reduction in STT-MRAM Caches by Selective Tag Comparison
Elham Cheshmikhani, Hamed Farbeh, Hossein Asad
Recent development in memory technologies has introduced Spin-Transfer Torque Magnetic RAM (STT-MRAM) as the most promising replacement for SRAMs in on-chip cache memories. Besides…
Modeling and Simulation Frameworks for Processing-in-Memory Architectures
Mahdi Aghaei, Saba Ebrahimi, Mohammad Saleh Arafati +4
Processing-in-Memory (PIM) has emerged as a promising computing paradigm to address the memory wall and the fundamental bottleneck of the von Neumann architecture by reducing costl…
CoPA: Cold Page Awakening to Overcome Retention Failures in STT-MRAM Based I/O Buffers
Mostafa Hadizadeh, Elham Cheshmikhani, Maysam Rahmanpour +2
Performance and reliability are two prominent factors in the design of data storage systems. To achieve higher performance, recently storage system designers use DRAM-based buffers…
TA-LRW: A Replacement Policy for Error Rate Reduction in STT-MRAM Caches
Elham Cheshmikhani, Hamed Farbeh, Seyed Ghassem Miremadi +1
As technology process node scales down, on-chip SRAM caches lose their efficiency because of their low scalability, high leakage power, and increasing rate of soft errors. Among em…
A System-Level Framework for Analytical and Empirical Reliability Exploration of STT-MRAM Caches
Elham Cheshmikhani, Hamed Farbeh, Hossein Asadi
Spin-Transfer Torque Magnetic RAM (STT-MRAM) is known as the most promising replacement for SRAM technology in large Last-Level Caches (LLCs). Despite its high-density, non-volatil…