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cs.AR2023
Yak: An Asynchronous Bundled Data Pipeline Description Language
Carsten Nielsen, Zhe Su, Giacomo Indiveri
The design of asynchronous circuits typically requires a judicious definition of signals and modules, combined with a proper specification of their timing constraints, which can be…
cs.AR2023
Core interface optimization for multi-core neuromorphic processors
Zhe Su, Hyunjung Hwang, Tristan Torchet +1
Hardware implementations of Spiking Neural Networks (SNNs) represent a promising approach to edge-computing for applications that require low-power and low-latency, and which canno…