activity
20222026
most citedA hardware-software co-design approach to minimize the use of memory resources in multi-core neuromorphic processors

1 citations · 1 across the 4 of their papers we have counts for

collaborators

5 papers

cs.ET2026

Small-World Communication Fabrics for Neuromorphic Multicore-SoCs

Sebastian Billaudelle, Christian Metzner, Jimmy Weber +7

As neuromorphic systems scale beyond a single core, inter-core event communication can become a dominant contributor to memory footprint, latency, and energy consumption. Biologica…

cs.AR2023

Yak: An Asynchronous Bundled Data Pipeline Description Language

Carsten Nielsen, Zhe Su, Giacomo Indiveri

The design of asynchronous circuits typically requires a judicious definition of signals and modules, combined with a proper specification of their timing constraints, which can be…

cs.AR2023

Core interface optimization for multi-core neuromorphic processors

Zhe Su, Hyunjung Hwang, Tristan Torchet +1

Hardware implementations of Spiking Neural Networks (SNNs) represent a promising approach to edge-computing for applications that require low-power and low-latency, and which canno…

cs.NE2022

Cortical-inspired placement and routing: minimizing the memory resources in multi-core neuromorphic processors

Vanessa R. C. Leite, Zhe Su, Adrian M. Whatley +1

Brain-inspired event-based neuromorphic processing systems have emerged as a promising technology in particular for bio-medical circuits and systems. However, both neuromorphic and…

cs.NE2022★ 1 cited

A hardware-software co-design approach to minimize the use of memory resources in multi-core neuromorphic processors

Vanessa R. C. Leite, Zhe Su, Adrian M. Whatley +1

Both in electronics and biology, physical implementations of neural networks have severe energy and memory constraints. We propose a hardware-software co-design approach for minimi…