1 citations · 2 across the 6 of their papers we have counts for
6 papers
Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs
Mingzhe Gao, Jieru Zhao, Zhe Lin +1
High-level synthesis (HLS) notably speeds up the hardware design process by avoiding RTL programming. However, the turnaround time of HLS increases significantly when post-route qu…
An Optimizing Framework on MLIR for Efficient FPGA-based Accelerator Generation
Weichuang Zhang, Jieru Zhao, Guan Shen +3
With the increasing demand for computing capability given limited resource and power budgets, it is crucial to deploy applications to customized accelerators like FPGAs. However, F…
FlowMap: Path Generation for Automated Vehicles in Open Space Using Traffic Flow
Wenchao Ding, Jieru Zhao, Yubin Chu +5
There is extensive literature on perceiving road structures by fusing various sensor inputs such as lidar point clouds and camera images using deep neural nets. Leveraging the late…
DataFlower: Exploiting the Data-flow Paradigm for Serverless Workflow Orchestration
Zijun Li, Chuhao Xu, Quan Chen +3
Serverless computing that runs functions with auto-scaling is a popular task execution pattern in the cloud-native era. By connecting serverless functions into workflows, tenants c…
SALO: An Efficient Spatial Accelerator Enabling Hybrid Sparse Attention Mechanisms for Long Sequences
Guan Shen, Jieru Zhao, Quan Chen +3
The attention mechanisms of transformers effectively extract pertinent information from the input sequence. However, the quadratic complexity of self-attention w.r.t the sequence l…
PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs
Zhe Lin, Zike Yuan, Jieru Zhao +3
Power estimation is the basis of many hardware optimization strategies. However, it is still challenging to offer accurate power estimation at an early stage such as high-level syn…