18 citations · 27 across the 8 of their papers we have counts for
8 papers
SoK: You Find What You Seek: Rethinking Oracles, Guidance, and Input Generation in Hardware Fuzzing
G Abarajithan, Zhenghua Ma, Cristian Tirelli +4
Hardware fuzzing is an active area in security verification research, yet its industrial adoption remains in its early stages. This SoK examines which lessons from software fuzzing…
Reliable edge machine learning hardware for scientific applications
Tommaso Baldi, Javier Campos, Ben Hawks +15
Extreme data rate scientific experiments create massive amounts of data that require efficient ML edge processing. This leads to unique validation challenges for VLSI implementatio…
Information Flow Coverage Metrics for Hardware Security Verification
Andres Meza, Ryan Kastner
Security graphs model attacks, defenses, mitigations, and vulnerabilities on computer networks and systems. With proper attributes, they provide security metrics using standard gra…
Pentimento: Data Remanence in Cloud FPGAs
Colin Drewes, Olivia Weng, Andres Meza +4
Cloud FPGAs strike an alluring balance between computational efficiency, energy efficiency, and cost. It is the flexibility of the FPGA architecture that enables these benefits, bu…
Tailor: Altering Skip Connections for Resource-Efficient Inference
Olivia Weng, Gabriel Marcano, Vladimir Loncar +7
Deep neural networks use skip connections to improve training convergence. However, these skip connections are costly in hardware, requiring extra buffers and increasing on- and of…
Open-source FPGA-ML codesign for the MLPerf Tiny Benchmark
Hendrik Borras, Giuseppe Di Guglielmo, Javier Duarte +15
We present our development experience and recent results for the MLPerf Tiny Inference Benchmark on field-programmable gate array (FPGA) platforms. We use the open-source hls4ml an…
AKER: A Design and Verification Framework for Safe andSecure SoC Access Control
Francesco Restuccia, Andres Meza, Ryan Kastner
Modern systems on a chip (SoCs) utilize heterogeneous architectures where multiple IP cores have concurrent access to on-chip shared resources. In security-critical applications, I…
Isadora: Automated Information Flow Property Generation for Hardware Designs
Calvin Deutschbein, Andres Meza, Francesco Restuccia +2
Isadora is a methodology for creating information flow specifications of hardware designs. The methodology combines information flow tracking and specification mining to produce a…