24 citations · 76 across the 18 of their papers we have counts for
9 papers · 1 filter
LocalTrain: Integer-Only Local Learning for Energy-Efficient CNN Training on Edge FPGAs
Shiqi Ding, Xuanyu Liang, Xinyang Liu +4
Local learning reduces cross-layer training dependencies, but an efficient accelerator must still retain operands, accumulate gradients, and select quantization scales. We present…
Alkaid: A Compiler Framework for Ultra-Low-Latency Kernels on Hardware
Chang Sun, Zhiqiang Que, Dimitrios Danopoulos +3
Ultra-low-latency machine learning and data processing pipelines operating on the sub-microsecond level often contain static dataflow kernels that require fine-grained bitwidth con…
HeteroReason: Heterogeneous FPGA-GPU Acceleration for Disaggregated Speculative Reasoning
Zehuan Zhang, Quan Deng, Zibo Ren +8
Large Reasoning Models (LRMs) have achieved state-of-the-art performance in reasoning tasks by utilizing Chain-of-Thought (CoT) reasoning. To achieve fast execution speed, speculat…
FQTree: Fine-grained Quantization and Hardware Generation of Boosted Decision Trees
Zhiqiang Que, Chang Sun, Haiyang Wang +6
Boosted decision trees (BDTs) are widely used in latency-critical applications, but efficient hardware deployment remains challenging. Existing designs often rely on uniform or man…
SPEAR: A System for Post-Quantization Error-Adaptive Recovery Enabling Efficient Low-Bit LLM Serving
Hongyuan Liu, Yawei Li, Zhiqiang Que +3
Efficient large language model (LLM) serving is increasingly constrained by deployment cost. Quantization is a key technique for reducing serving cost, yet even state-of-the-art 4-…
HGQ-LUT: Fast LUT-Aware Training and Efficient Architectures for DNN Inference
Chang Sun, Zhiqiang Que, Bakhtiar Zadeh +4
Lookup-table (LUT) based neural networks can deliver ultra-low latency and excellent hardware efficiency on FPGAs by mapping arithmetic operations directly onto the logic primitive…
da4ml: Distributed Arithmetic for Real-time Neural Networks on FPGAs
Chang Sun, Zhiqiang Que, Vladimir Loncar +2
Neural networks with a latency requirement on the order of microseconds, like the ones used at the CERN Large Hadron Collider, are typically deployed on FPGAs fully unrolled and pi…
MetaML-Pro: Cross-Stage Design Flow Automation for Efficient Deep Learning Acceleration
Zhiqiang Que, Jose G. F. Coutinho, Ce Guo +2
This paper presents a unified framework for codifying and automating optimization strategies to efficiently deploy deep neural networks (DNNs) on resource-constrained hardware, suc…
LL-GNN: Low Latency Graph Neural Networks on FPGAs for High Energy Physics
Zhiqiang Que, Hongxiang Fan, Marcus Loo +5
This work presents a novel reconfigurable architecture for Low Latency Graph Neural Network (LL-GNN) designs for particle detectors, delivering unprecedented low latency performanc…