da4ml: Distributed Arithmetic for Real-time Neural Networks on FPGAs
arXiv:2507.04535 · doi:10.1145/3777387
Abstract
Neural networks with a latency requirement on the order of microseconds, like the ones used at the CERN Large Hadron Collider, are typically deployed on FPGAs fully unrolled and pipelined. A bottleneck for the deployment of such neural networks is area utilization, which is directly related to the required constant matrix-vector multiplication (CMVM) operations. In this work, we propose an efficient algorithm for implementing CMVM operations with distributed arithmetic on FPGAs that simultaneously optimizes for area consumption and latency. The algorithm achieves resource reduction similar to state-of-the-art algorithms while being significantly faster to compute. The proposed algorithm is open-sourced and integrated into the \texttt{hls4ml} library, a free and open-source library for running real-time neural network inference on FPGAs. We show that the proposed algorithm can reduce on-chip resources by up to a third for realistic, highly quantized neural networks while simultaneously reducing latency, enabling the implementation of previously infeasible networks.
References in corpus (12)
- Automatic heterogeneous quantization of deep neural networks for low-latency inference on the edge for particle detectors
- Fast convolutional neural networks on FPGAs with hls4ml
- Autoencoders on FPGAs for real-time, unsupervised new physics detection at 40 MHz at the Large Hadron Collider
- Real-time Neural Network Inference on Extremely Weak Devices: Agile Offloading with Explainable AI
- Accelerating Recurrent Neural Networks for Gravitational Wave Experiments
- LL-GNN: Low Latency Graph Neural Networks on FPGAs for High Energy Physics
- TreeLUT: An Efficient Alternative to Deep Neural Networks for Inference Acceleration Using Gradient Boosted Decision Trees
- NeuraLUT: Hiding Neural Network Density in Boolean Synthesizable Functions
- Fast Muon Tracking with Machine Learning Implemented in FPGA
- Ultrafast jet classification on FPGAs for the HL-LHC
- FPGA Resource-aware Structured Pruning for Real-Time Neural Networks
- Fast Jet Tagging with MLP-Mixers on FPGAs