2 citations · 4 across the 8 of their papers we have counts for
8 papers
RACAM: Enhancing DRAM with Reuse-Aware Computation and Automated Mapping for ML Inference
Siyuan Ma, Jiajun Hu, Jeeho Ryoo +2
In-DRAM Processing-In-Memory (DRAM-PIM) has emerged as a promising approach to accelerate memory-intensive workloads by mitigating data transfer overhead between DRAM and the host…
PIMSAB: A Processing-In-Memory System with Spatially-Aware Communication and Bit-Serial-Aware Computation
Aman Arora, Jian Weng, Siyuan Ma +2
Bit-serial Processing-In-Memory (PIM) is an attractive paradigm for accelerator architectures, for parallel workloads such as Deep Learning (DL), because of its capability to achie…
ULEEN: A Novel Architecture for Ultra Low-Energy Edge Neural Networks
Zachary Susskind, Aman Arora, Igor D. S. Miranda +9
The deployment of AI models on low-power, real-time edge devices requires accelerators for which energy, latency, and area are all first-order concerns. There are many approaches t…
HLSDataset: Open-Source Dataset for ML-Assisted FPGA Design using High Level Synthesis
Zhigang Wei, Aman Arora, Ruihao Li +1
Machine Learning (ML) has been widely adopted in design exploration using high level synthesis (HLS) to give a better and faster performance, and resource and power estimation at v…
CoMeFa: Compute-in-Memory Blocks for FPGAs
Aman Arora, Tanmay Anand, Aatman Borda +4
Block RAMs (BRAMs) are the storage houses of FPGAs, providing extensive on-chip memory bandwidth to the compute units implemented using Logic Blocks (LBs) and Digital Signal Proces…
Weightless Neural Networks for Efficient Edge Inference
Zachary Susskind, Aman Arora, Igor Dantas Dos Santos Miranda +8
Weightless Neural Networks (WNNs) are a class of machine learning model which use table lookups to perform inference. This is in contrast with Deep Neural Networks (DNNs), which us…
Compute RAMs: Adaptable Compute and Storage Blocks for DL-Optimized FPGAs
Aman Arora, Bagus Hanindhito, Lizy K. John
The configurable building blocks of current FPGAs -- Logic blocks (LBs), Digital Signal Processing (DSP) slices, and Block RAMs (BRAMs) -- make them efficient hardware accelerators…
Koios: A Deep Learning Benchmark Suite for FPGA Architecture and CAD Research
Aman Arora, Andrew Boutros, Daniel Rauch +9
With the prevalence of deep learning (DL) in many applications, researchers are investigating different ways of optimizing FPGA architecture and CAD to achieve better quality-of-re…