19 citations · 34 across the 11 of their papers we have counts for
6 papers · 1 filter
IOPS: An Unified SpMM Accelerator Based on Inner-Outer-Hybrid Product
Wenhao Sun, Wendi Sun, Song Chen +1
Sparse matrix multiplication (SpMM) is widely applied to numerous domains, such as graph processing, machine learning, and data analytics. However, inner product based SpMM induces…
Graph Attention-Based Symmetry Constraint Extraction for Analog Circuits
Qi Xu, Lijie Wang, Jing Wang +3
In recent years, analog circuits have received extensive attention and are widely used in many emerging applications. The high demand for analog circuits necessitates shorter circu…
YOCO: A Hybrid In-Memory Computing Architecture with 8-bit Sub-PetaOps/W In-Situ Multiply Arithmetic for Large-Scale AI
Zihao Xuan, Yuxuan Yang, Wei Xuan +3
In this paper, we further explore the potential of analog in-memory computing (AiMC) and introduce an innovative artificial intelligence (AI) accelerator architecture named YOCO, f…
BandMap: Application Mapping with Bandwidth Allocation forCoarse-Grained Reconfigurable Array
Xiaobing Ni, Jiaheng Ruan, Mengke Ge +3
This paper proposes an application mapping algorithm, BandMap, for coarse-grained reconfigurable array (CGRA), which allocates the bandwidth in PE array according to the transferri…
NicePIM: Design Space Exploration for Processing-In-Memory DNN Accelerators with 3D-Stacked-DRAM
Junpeng Wang, Mengke Ge, Bo Ding +3
With the widespread use of deep neural networks(DNNs) in intelligent systems, DNN accelerators with high performance and energy efficiency are greatly demanded. As one of the feasi…
Bit-balance: Model-Hardware Co-design for Accelerating NNs by Exploiting Bit-level Sparsity
Wenhao Sun, Zhiwei Zou, Deng Liu +3
Bit-serial architectures can handle Neural Networks (NNs) with different weight precisions, achieving higher resource efficiency compared with bit-parallel architectures. Besides,…