19 citations · 34 across the 11 of their papers we have counts for
11 papers
SparseMap: Loop Mapping for Sparse CNNs on Streaming Coarse-grained Reconfigurable Array
Xiaobing Ni, Mengke Ge, Jiaheng Ruan +2
Streaming coarse-grained reconfgurable array (CGRA) is a promising architecture for data/computing-intensive applications because of its fexibility, high throughput and efcient mem…
Allspark: Workload Orchestration for Visual Transformers on Processing In-Memory Systems
Mengke Ge, Junpeng Wang, Binhan Chen +4
The advent of Transformers has revolutionized computer vision, offering a powerful alternative to convolutional neural networks (CNNs), especially with the local attention mechanis…
IOPS: An Unified SpMM Accelerator Based on Inner-Outer-Hybrid Product
Wenhao Sun, Wendi Sun, Song Chen +1
Sparse matrix multiplication (SpMM) is widely applied to numerous domains, such as graph processing, machine learning, and data analytics. However, inner product based SpMM induces…
Graph Attention-Based Symmetry Constraint Extraction for Analog Circuits
Qi Xu, Lijie Wang, Jing Wang +3
In recent years, analog circuits have received extensive attention and are widely used in many emerging applications. The high demand for analog circuits necessitates shorter circu…
YOCO: A Hybrid In-Memory Computing Architecture with 8-bit Sub-PetaOps/W In-Situ Multiply Arithmetic for Large-Scale AI
Zihao Xuan, Yuxuan Yang, Wei Xuan +3
In this paper, we further explore the potential of analog in-memory computing (AiMC) and introduce an innovative artificial intelligence (AI) accelerator architecture named YOCO, f…
BandMap: Application Mapping with Bandwidth Allocation forCoarse-Grained Reconfigurable Array
Xiaobing Ni, Jiaheng Ruan, Mengke Ge +3
This paper proposes an application mapping algorithm, BandMap, for coarse-grained reconfigurable array (CGRA), which allocates the bandwidth in PE array according to the transferri…
NicePIM: Design Space Exploration for Processing-In-Memory DNN Accelerators with 3D-Stacked-DRAM
Junpeng Wang, Mengke Ge, Bo Ding +3
With the widespread use of deep neural networks(DNNs) in intelligent systems, DNN accelerators with high performance and energy efficiency are greatly demanded. As one of the feasi…
Bit-balance: Model-Hardware Co-design for Accelerating NNs by Exploiting Bit-level Sparsity
Wenhao Sun, Zhiwei Zou, Deng Liu +3
Bit-serial architectures can handle Neural Networks (NNs) with different weight precisions, achieving higher resource efficiency compared with bit-parallel architectures. Besides,…
Task modules Partitioning, Scheduling and Floorplanning for Partially Dynamically Reconfigurable Systems Based on Modern Heterogeneous FPGAs
Bo Ding, Jinglei Huang, Junpeng Wang +3
Modern field programmable gate array(FPGA) can be partially dynamically reconfigurable with heterogeneous resources distributed on the chip. And FPGA-based partially dynamically re…
Sense: Model Hardware Co-design for Accelerating Sparse CNN on Systolic Array
Wenhao Sun, Deng Liu, Zhiwei Zou +3
Sparsity is an intrinsic property of convolutional neural network(CNN) and worth exploiting for CNN accelerators, but extra processing comes with hardware overhead, causing many ar…
Synthesizing Brain-Network-Inspired Interconnections for Large-Scale Network-on-Chips
Mengke Ge, Xiaobing Ni, Qi Xu +4
Brain network is a large-scale complex network with scale-free, small-world, and modularity properties, which largely supports this high-efficiency massive system. In this paper, w…