4 citations · 4 across the 9 of their papers we have counts for
11 papers · 1 filter
FAME: An FPGA-Based Platform for Approximate Multipliers Evaluation with Pattern-Guided DNN Retraining
Rappy Saha, Nima Amirafshar, Jude Haris +2
Approximate multipliers can reduce hardware area and energy consumption in Deep Neural Network (DNN) inference; however, they introduce computational errors. Assessing the accuracy…
FlexViT: A Flexible FPGA-based Accelerator for Edge Vision Transformers
Hubert Dymarkowski, Xingjian Fu, Rappy Saha +2
Deploying Vision Transformer (ViT) models on edge platforms remains challenging due to their high computational demands and the architectural heterogeneity of modern hybrid ViT mod…
Defeat the Heap: Zero-Copy Data Movement in AXI4MLIR
Elam Cohavi, Nicolas Bohm Agostini, Jude Haris +3
As custom hardware accelerators become increasingly central to machine learning workloads, efficient data transfer is critical for maximizing accelerator performance on linear alge…
Towards Autonomous Accelerator Design: FPGA Accelerator Generation with SECDA
Vinamra Sharma, Xingjian Fu, Jude Haris +1
Designing FPGA-based accelerators for modern artificial intelligence workloads requires exploring a large and complex hardware design space that involves architectural parameters,…
PoTAcc: A Pipeline for End-to-End Acceleration of Power-of-Two Quantized DNNs
Rappy Saha, Jude Haris, Nicolas Bohm Agostini +2
Power-of-two (PoT) quantization significantly reduces the size of deep neural networks (DNNs) and replaces multiplications with bit-shift operations for inference. Prior work has s…
LLM-Driven Design Space Exploration of FPGA-based Accelerators
Vinamra Sharma, Xingjian Fu, Jude Haris +1
Designing field-programmable gate array (FPGA)-based accelerators for modern artificial intelligence workloads requires navigating a large and complex hardware design space encompa…