4 citations · 7 across the 12 of their papers we have counts for
13 papers
FAME: An FPGA-Based Platform for Approximate Multipliers Evaluation with Pattern-Guided DNN Retraining
Rappy Saha, Nima Amirafshar, Jude Haris +2
Approximate multipliers can reduce hardware area and energy consumption in Deep Neural Network (DNN) inference; however, they introduce computational errors. Assessing the accuracy…
FlexViT: A Flexible FPGA-based Accelerator for Edge Vision Transformers
Hubert Dymarkowski, Xingjian Fu, Rappy Saha +2
Deploying Vision Transformer (ViT) models on edge platforms remains challenging due to their high computational demands and the architectural heterogeneity of modern hybrid ViT mod…
Defeat the Heap: Zero-Copy Data Movement in AXI4MLIR
Elam Cohavi, Nicolas Bohm Agostini, Jude Haris +3
As custom hardware accelerators become increasingly central to machine learning workloads, efficient data transfer is critical for maximizing accelerator performance on linear alge…
Towards Autonomous Accelerator Design: FPGA Accelerator Generation with SECDA
Vinamra Sharma, Xingjian Fu, Jude Haris +1
Designing FPGA-based accelerators for modern artificial intelligence workloads requires exploring a large and complex hardware design space that involves architectural parameters,…
PoTAcc: A Pipeline for End-to-End Acceleration of Power-of-Two Quantized DNNs
Rappy Saha, Jude Haris, Nicolas Bohm Agostini +2
Power-of-two (PoT) quantization significantly reduces the size of deep neural networks (DNNs) and replaces multiplications with bit-shift operations for inference. Prior work has s…
LLM-Driven Design Space Exploration of FPGA-based Accelerators
Vinamra Sharma, Xingjian Fu, Jude Haris +1
Designing field-programmable gate array (FPGA)-based accelerators for modern artificial intelligence workloads requires navigating a large and complex hardware design space encompa…
F-BFQ: Flexible Block Floating-Point Quantization Accelerator for LLMs
Jude Haris, José Cano
Large Language Models (LLMs) have become increasingly prominent for daily tasks, from improving sound-totext translation to generating additional frames for the latest video games.…
Accelerating Transposed Convolutions on FPGA-based Edge Devices
Jude Haris, José Cano
Transposed Convolutions (TCONV) enable the up-scaling mechanism within generative Artificial Intelligence (AI) models. However, the predominant Input-Oriented Mapping (IOM) method…
Accelerating PoT Quantization on Edge Devices
Rappy Saha, Jude Haris, José Cano
Non-uniform quantization, such as power-of-two (PoT) quantization, matches data distributions better than uniform quantization, which reduces the quantization error of Deep Neural…
Designing Efficient LLM Accelerators for Edge Devices
Jude Haris, Rappy Saha, Wenhao Hu +1
The increase in open-source availability of Large Language Models (LLMs) has enabled users to deploy them on more and more resource-constrained edge devices to reduce reliance on n…
Data Transfer Optimizations for Host-CPU and Accelerators in AXI4MLIR
Jude Haris, Nicolas Bohm Agostini, Antonino Tumeo +2
As custom hardware accelerators become more prevalent, it becomes increasingly important to automatically generate efficient host-driver code that can fully leverage the capabiliti…
AXI4MLIR: User-Driven Automatic Host Code Generation for Custom AXI-Based Accelerators
Nicolas Bohm Agostini, Jude Haris, Perry Gibson +6
This paper addresses the need for automatic and efficient generation of host driver code for arbitrary custom AXI-based accelerators targeting linear algebra algorithms, an importa…
SECDA: Efficient Hardware/Software Co-Design of FPGA-based DNN Accelerators for Edge Inference
Jude Haris, Perry Gibson, José Cano +2
Edge computing devices inherently face tight resource constraints, which is especially apparent when deploying Deep Neural Networks (DNN) with high memory and compute demands. FPGA…