1 citations · 1 across the 2 of their papers we have counts for
7 papers
CXLAimPod: CXL Memory is all you need in AI era
Yiwei Yang, Yusheng Zheng, Yiqi Chen +5
The proliferation of data-intensive applications, ranging from large language models to key-value stores, increasingly stresses memory systems with mixed read-write access patterns…
FPGA-based Emulation and Device-Side Management for CXL-based Memory Tiering Systems
Yiqi Chen, Xiping Dong, Zhe Zhou +3
The Compute Express Link (CXL) technology facilitates the extension of CPU memory through byte-addressable SerDes links and cascaded switches, creating complex heterogeneous memory…
Enabling Efficient Transaction Processing on CXL-Based Memory Sharing
Zhao Wang, Yiqi Chen, Cong Li +5
Transaction processing systems are the crux for modern data-center applications, yet current multi-node systems are slow due to network overheads. This paper advocates for Compute…
Theseus: Exploring Efficient Wafer-Scale Chip Design for Large Language Models
Jingchen Zhu, Chenhao Xue, Yiqi Chen +13
The emergence of the large language model~(LLM) poses an exponential growth of demand for computation throughput, memory capacity, and communication bandwidth. Such a demand growth…
The Dawn of AI-Native EDA: Opportunities and Challenges of Large Circuit Models
Lei Chen, Yiqi Chen, Zhufei Chu +36
Within the Electronic Design Automation (EDA) domain, AI-driven solutions have emerged as formidable tools, yet they typically augment rather than redefine existing methodologies.…
NeoMem: Hardware/Software Co-Design for CXL-Native Memory Tiering
Zhe Zhou, Yiqi Chen, Tao Zhang +8
The Compute Express Link (CXL) interconnect makes it feasible to integrate diverse types of memory into servers via its byte-addressable SerDes links. Considering the various acces…