77 citations · 100 across the 9 of their papers we have counts for
3 papers · 1 filter
Development of LGAD Sensor Technology on 12 inch Wafers for 3D Integration with advanced CMOS processes
Ron Lipton, Julie Segal, Angela Kok +10
We report on the design, simulation, and initial testing of Low Gain Avalanche Diode (LGAD) sensors fabricated in 65 nm CMOS technology on 12 inch wafers. These sensors were develo…
PSEC6: an 8-Channel 40 GSa/s Waveform Sampling ASIC in TSMC 65nm with 10.24 GHz PLL
Ahan Datta, Andrew Arzac, Davide Braga +14
Picosecond level timing resolution is a prerequisite capability for improved coincidence matching, time-of-flight measurements, and secondary vertex reconstruction. Here, we presen…
A Sub-electron-noise Skipper-CCD Readout ASIC with Improved Channel-to-channel Isolation and an Integrated Cryogenic Voltage Reference
Fabricio Alcalde Bessia, Claudio Chavez, Troy England +6
The MIDNA application specific integrated circuits (ASICs) are a series of skipper-CCD readout chips fabricated in a 65 nm low-power CMOS process that implement a correlated double…