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cs.AR2024
CIS: Composable Instruction Set for Data Streaming Applications
Yu Yang, Jordi Altayó González, Paul Delestrac +1
The enhanced efficiency of hardware accelerators, including Single Instruction Multiple Data (SIMD) architectures and Coarse-Grained Reconfigurable Architectures (CGRAs), is drivin…
cs.AR2021
Synthesis of Predictable Global NoC by Abutment in Synchoros VLSI Design
Jordi Altayó González, Dimitrios Stathis, Ahmed Hemani
Synchoros VLSI design style has been proposed as an alternative to the standard cell best design style; the word synchoros is derived from the Greek word choros for space. Synchori…
cs.AR2019
Refresh Triggered Computation: Improving the Energy Efficiency of Convolutional Neural Network Accelerators
Syed M. A. H. Jafri, Hasan Hassan, Ahmed Hemani +1
To employ a Convolutional Neural Network (CNN) in an energy-constrained embedded system, it is critical for the CNN implementation to be highly energy efficient. Many recent studie…