activity
20192024
most citedeBrainII: A 3 kW Realtime Custom 3D DRAM integrated ASIC implementation of a Biologically Plausible Model of a Human Scale Cortex

15 citations · 21 across the 6 of their papers we have counts for

collaborators

7 papers

cs.AR2024

CIS: Composable Instruction Set for Data Streaming Applications

Yu Yang, Jordi Altayó González, Paul Delestrac +1

The enhanced efficiency of hardware accelerators, including Single Instruction Multiple Data (SIMD) architectures and Coarse-Grained Reconfigurable Architectures (CGRAs), is drivin…

cs.AR2022★ 2 cited

Vesyla-II: An Algorithm Library Development Tool for Synchoros VLSI Design Style

Yu Yang, Ahmed Hemani

High-level synthesis (HLS) has been researched for decades and is still limited to fast FPGA prototyping and algorithmic RTL generation. A feasible end-to-end system-level synthesi…

cs.AR2021

Synthesis of Predictable Global NoC by Abutment in Synchoros VLSI Design

Jordi Altayó González, Dimitrios Stathis, Ahmed Hemani

Synchoros VLSI design style has been proposed as an alternative to the standard cell best design style; the word synchoros is derived from the Greek word choros for space. Synchori…

cs.LG2021

MOHAQ: Multi-Objective Hardware-Aware Quantization of Recurrent Neural Networks

Nesma M. Rezk, Tomas Nordström, Dimitrios Stathis +3

The compression of deep learning models is of fundamental importance in deploying such models to edge devices. The selection of compression parameters can be automated to meet chan…

cs.DC2019★ 15 cited

eBrainII: A 3 kW Realtime Custom 3D DRAM integrated ASIC implementation of a Biologically Plausible Model of a Human Scale Cortex

Dimitrios Stathis, Chirag Sudarshan, Yu Yang +6

The Artificial Neural Networks (ANNs) like CNN/DNN and LSTM are not biologically plausible and in spite of their initial success, they cannot attain the cognitive capabilities enab…

cs.AR2019

Clock Tree Generation by Abutment in Synchoros VLSI Design

Dimitrios Stathis, Panagiotis Chaourani, Syed M. A. H. Jafri +1

Synchoros VLSI design style has been proposed as an alternative to standard cell-based design. Standard cells are replaced by synchoros, large grain, VLSI design objects called SiL…

cs.AR2019★ 4 cited

Refresh Triggered Computation: Improving the Energy Efficiency of Convolutional Neural Network Accelerators

Syed M. A. H. Jafri, Hasan Hassan, Ahmed Hemani +1

To employ a Convolutional Neural Network (CNN) in an energy-constrained embedded system, it is critical for the CNN implementation to be highly energy efficient. Many recent studie…