2 papers
cs.AR2022
Scale-out Systolic Arrays
Ahmet Caner Yüzügüler, Canberk Sönmez, Mario Drumond +3
Multi-pod systolic arrays are emerging as the architecture of choice in DNN inference accelerators. Despite their potential, designing multi-pod systolic arrays to maximize effecti…
cs.AR2020
Enabling High-Capacity, Latency-Tolerant, and Highly-Concurrent GPU Register Files via Software/Hardware Cooperation
Mohammad Sadrosadati, Amirhossein Mirhosseini, Ali Hajiabadi +7
Graphics Processing Units (GPUs) employ large register files to accommodate all active threads and accelerate context switching. Unfortunately, register files are a scalability bot…