22 citations · 45 across the 27 of their papers we have counts for
10 papers · 1 filter
FERMI-ML: A Flexible and Resource-Efficient Memory-In-Situ SRAM Macro for TinyML acceleration
Mukul Lokhande, Akash Sankhe, S. V. Jaya Chand +1
The growing demand for low-power and area-efficient TinyML inference on AIoT devices necessitates memory architectures that minimise data movement while sustaining high computation…
RAMAN: Resource-efficient ApproxiMate Posit Processing for Algorithm-Hardware Co-desigN
Mohd Faisal Khan, Mukul Lokhande, Santosh Kumar Vishvakarma
Edge-AI applications still face considerable challenges in enhancing computational efficiency in resource-constrained environments. This work presents RAMAN, a resource-efficient a…
Res-DPU: Resource-shared Digital Processing-in-memory Unit for Edge-AI Workloads
Mukul Lokhande, Narendra Singh Dhakad, Seema Chouhan +2
Processing-in-memory (PIM) has emerged as the go to solution for addressing the von Neumann bottleneck in edge AI accelerators. However, state-of-the-art (SoTA) digital PIM approac…
Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation
Mukul Lokhande, Tanushree Dewangan, Mohd Sharik Mansoori +5
This paper introduces Bhasha-Rupantarika, a light and efficient multilingual translation system tailored through algorithm-hardware codesign for resource-limited settings. The meth…
ReLANCE: A Resource-Efficient Low-Latency Cortical Neural Acceleration Engine
Sonu Kumar, Arjun S. Nair, Bhawna Chaudhary +2
We present a Cortical Neural Pool (CNP) architecture featuring a high-speed, resource-efficient CORDIC based Hodgkin-Huxley (RCHH) neuron model. Unlike shared CORDIC-based DNN appr…
XR-NPE: High-Throughput Mixed-precision SIMD Neural Processing Engine for Extended Reality Perception Workloads
Tejas Chaudhari, Akarsh J., Tanushree Dewangan +2
This work proposes XR-NPE, a high-throughput Mixed-precision SIMD Neural Processing Engine, designed for extended reality (XR) perception workloads like visual inertial odometry (V…
POLARON: Precision-aware On-device Learning and Adaptive Runtime-cONfigurable AI acceleration
Mukul Lokhande, Santosh Kumar Vishvakarma
The increasing complexity of AI models requires flexible hardware capable of supporting diverse precision formats, particularly for energy-constrained edge platforms. This work pre…
QForce-RL: Quantized FPGA-Optimized Reinforcement Learning Compute Engine
Anushka Jha, Tanushree Dewangan, Mukul Lokhande +1
Reinforcement Learning (RL) has outperformed other counterparts in sequential decision-making and dynamic environment control. However, FPGA deployment is significantly resource-ex…
Retrospective: A CORDIC Based Configurable Activation Function for NN Applications
Omkar Kokane, Gopal Raut, Salim Ullah +4
A CORDIC-based configuration for the design of Activation Functions (AF) was previously suggested to accelerate ASIC hardware design for resource-constrained systems by providing f…
CORDIC Is All You Need
Omkar Kokane, Adam Teman, Anushka Jha +6
Artificial intelligence necessitates adaptable hardware accelerators for efficient high-throughput million operations. We present pipelined architecture with CORDIC block for linea…