22 citations · 45 across the 27 of their papers we have counts for
28 papers
SPARX: Secure and Privacy-Aware Approximate CNN Acceleration with Edge RISC-V SoC
Sonu Kumar, Akash Sankhe, Mukul Lokhande +1
Edge-AI systems increasingly require real-time CNN inference under strict energy, performance, security, and privacy constraints. Approximate computing improves hardware efficiency…
E-ReCON: An Energy- and Resource-Efficient Precision-Configurable Sparse nvCIM Macro for Conventional and Spiking Neural Edge Inference
Ankit Kumar Tenwar, Mukul Lokhande, Santosh Kumar Vishvakarma
This work presents E-ReCON, a 16 Kb energy and resource-efficient digital compute-in-memory (DCIM) macro based on a compact 3T1R ReRAM bitcell for edge-AI inference. The proposed b…
ADS-IMC: Accelerating Data Sorting with In-Memory Computation
Narendra Singh Dhakad, Santosh Kumar Vishvakarma
Sorting is a fundamental operation across numerous computational domains. Traditionally, this process involves transferring data from main memory to a processing unit for sorting,…
SRAM Based Digital Custom Compute Engine for Improved Area Efficiency of AI Hardware
Narendra Singh Dhakad, Santosh Kumar Vishvakarma
This paper presents a novel architecture utilizing a 10T SRAM cell for XNOR-based in-memory computing, aimed at mitigating the extensive routing challenges typically encountered in…
TREA: Low-precision Time-Multiplexed, Resource-Efficient Edge Accelerator for Object Detection and Classification
Vijay Pratap Sharma, Mukul Lokhande, Ratko Pilipovic +2
This work presents TREA, a low-precision time-multiplexed and resource-efficient edge-AI accelerator for object detection and classification, targeting stringent area-power-latency…
CARMEN: CORDIC-Accelerated Resource-Efficient Multi-Precision Inference Engine for Deep Learning
Sonu Kumar, Mukul Lokhande, Santosh Kumar Vishvakarma +1
This paper presents CARMEN, a runtime-adaptive, CORDIC-accelerated multi-precision vector engine for resource-efficient deep learning inference. The key insight is that CORDIC iter…
EULER-ADAS: Energy-Efficient & SIMD-Unified Logarithmic-Posit Engine for Precision-Reconfigurable Approximate ADAS Acceleration
Mukul Lokhande, Ratko Pilipovic, Omkar Kokane +2
Advanced driver-assistance systems (ADAS) require neural compute engines that deliver low-latency inference under strict power and area constraints. Posit arithmetic is attractive…
DHFP-PE: Dual-Precision Hybrid Floating Point Processing Element for AI Acceleration
Shubham Kumar, Vijay Pratap Sharma, Vaibhav Neema +1
The rapid adoption of low-precision arithmetic in artificial intelligence and edge computing has created a strong demand for energy-efficient and flexible floating-point multiply-a…
L-SPINE: A Low-Precision SIMD Spiking Neural Compute Engine for Resource-efficient Edge Inference
Sonu Kumar, Mukul Lokhande, Santosh Kumar Vishvakarma
Spiking Neural Networks (SNNs) offer a promising solution for energy-efficient edge intelligence; however, their hardware deployment is constrained by memory overhead, inefficient…
CORVET: A CORDIC-Powered, Resource-Frugal Mixed-Precision Vector Processing Engine for High-Throughput AIoT applications
Sonu Kumar, Mohd Faisal Khan, Mukul Lokhande +1
This brief presents a runtime-adaptive, performance-enhanced vector engine featuring a low-resource, iterative CORDIC-based MAC unit for edge AI acceleration. The proposed design e…
SPADE: A SIMD Posit-enabled compute engine for Accelerating DNN Efficiency
Sonu Kumar, Lavanya Vinnakota, Mukul Lokhande +2
The growing demand for edge-AI systems requires arithmetic units that balance numerical precision, energy efficiency, and compact hardware while supporting diverse formats. Posit a…
Bio-RV: Low-Power Resource-Efficient RISC-V Processor for Biomedical Applications
Vijay Pratap Sharma, Annu Kumar, Mohd Faisal Khan +2
This work presents Bio-RV, a compact and resource-efficient RISC-V processor intended for biomedical control applications, such as accelerator-based biomedical SoCs and implantable…
FERMI-ML: A Flexible and Resource-Efficient Memory-In-Situ SRAM Macro for TinyML acceleration
Mukul Lokhande, Akash Sankhe, S. V. Jaya Chand +1
The growing demand for low-power and area-efficient TinyML inference on AIoT devices necessitates memory architectures that minimise data movement while sustaining high computation…
RAMAN: Resource-efficient ApproxiMate Posit Processing for Algorithm-Hardware Co-desigN
Mohd Faisal Khan, Mukul Lokhande, Santosh Kumar Vishvakarma
Edge-AI applications still face considerable challenges in enhancing computational efficiency in resource-constrained environments. This work presents RAMAN, a resource-efficient a…
Res-DPU: Resource-shared Digital Processing-in-memory Unit for Edge-AI Workloads
Mukul Lokhande, Narendra Singh Dhakad, Seema Chouhan +2
Processing-in-memory (PIM) has emerged as the go to solution for addressing the von Neumann bottleneck in edge AI accelerators. However, state-of-the-art (SoTA) digital PIM approac…
Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation
Mukul Lokhande, Tanushree Dewangan, Mohd Sharik Mansoori +5
This paper introduces Bhasha-Rupantarika, a light and efficient multilingual translation system tailored through algorithm-hardware codesign for resource-limited settings. The meth…
ReLANCE: A Resource-Efficient Low-Latency Cortical Neural Acceleration Engine
Sonu Kumar, Arjun S. Nair, Bhawna Chaudhary +2
We present a Cortical Neural Pool (CNP) architecture featuring a high-speed, resource-efficient CORDIC based Hodgkin-Huxley (RCHH) neuron model. Unlike shared CORDIC-based DNN appr…
XR-NPE: High-Throughput Mixed-precision SIMD Neural Processing Engine for Extended Reality Perception Workloads
Tejas Chaudhari, Akarsh J., Tanushree Dewangan +2
This work proposes XR-NPE, a high-throughput Mixed-precision SIMD Neural Processing Engine, designed for extended reality (XR) perception workloads like visual inertial odometry (V…
POLARON: Precision-aware On-device Learning and Adaptive Runtime-cONfigurable AI acceleration
Mukul Lokhande, Santosh Kumar Vishvakarma
The increasing complexity of AI models requires flexible hardware capable of supporting diverse precision formats, particularly for energy-constrained edge platforms. This work pre…
QForce-RL: Quantized FPGA-Optimized Reinforcement Learning Compute Engine
Anushka Jha, Tanushree Dewangan, Mukul Lokhande +1
Reinforcement Learning (RL) has outperformed other counterparts in sequential decision-making and dynamic environment control. However, FPGA deployment is significantly resource-ex…
Retrospective: A CORDIC Based Configurable Activation Function for NN Applications
Omkar Kokane, Gopal Raut, Salim Ullah +4
A CORDIC-based configuration for the design of Activation Functions (AF) was previously suggested to accelerate ASIC hardware design for resource-constrained systems by providing f…
CORDIC Is All You Need
Omkar Kokane, Adam Teman, Anushka Jha +6
Artificial intelligence necessitates adaptable hardware accelerators for efficient high-throughput million operations. We present pipelined architecture with CORDIC block for linea…
Flex-PE: Flexible and SIMD Multi-Precision Processing Element for AI Workloads
Mukul Lokhande, Gopal Raut, Santosh Kumar Vishvakarma
The rapid adaptation of data driven AI models, such as deep learning inference, training, Vision Transformers (ViTs), and other HPC applications, drives a strong need for runtime p…
HYDRA: Hybrid Data Multiplexing and Run-time Layer Configurable DNN Accelerator
Sonu Kumar, Komal Gupta, Gopal Raut +2
Deep neural networks (DNNs) offer plenty of challenges in executing efficient computation at edge nodes, primarily due to the huge hardware resource demands. The article proposes H…