4 citations · 4 across the 5 of their papers we have counts for
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cs.AR2007
Power-Performance Trade-Offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage
Robert Bai, Nam-Sung Kim, Tae Ho Kgil +2
In this paper, we investigate the impact of T_{ox} and Vth on power performance trade-offs for on-chip caches. We start by examining the optimization of the various components of a…
cs.AR2007
DVS for On-Chip Bus Designs Based on Timing Error Correction
Himanshu Kaul, Dennis Sylvester, David Blaauw +2
On-chip buses are typically designed to meet performance constraints at worst-case conditions, including process corner, temperature, IR-drop, and neighboring net switching pattern…