4 citations · 4 across the 5 of their papers we have counts for
5 papers
Accelerating Graph Analytics on a Reconfigurable Architecture with a Data-Indirect Prefetcher
Yichen Yang, Jingtao Li, Nishil Talati +5
The irregular nature of memory accesses of graph workloads makes their performance poor on modern computing platforms. On manycore reconfigurable architectures (MRAs), in particula…
Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm
Sung Kim, Morteza Fayazi, Alhad Daftardar +10
We present Versa, an energy-efficient processor with 36 systolic ARM Cortex-M4F cores and a runtime-reconfigurable memory hierarchy. Versa exploits algorithm-specific characteristi…
CoDR: Computation and Data Reuse Aware CNN Accelerator
Alireza Khadem, Haojie Ye, Trevor Mudge
Computation and Data Reuse is critical for the resource-limited Convolutional Neural Network (CNN) accelerators. This paper presents Universal Computation Reuse to exploit weight s…
Power-Performance Trade-Offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage
Robert Bai, Nam-Sung Kim, Tae Ho Kgil +2
In this paper, we investigate the impact of T_{ox} and Vth on power performance trade-offs for on-chip caches. We start by examining the optimization of the various components of a…
DVS for On-Chip Bus Designs Based on Timing Error Correction
Himanshu Kaul, Dennis Sylvester, David Blaauw +2
On-chip buses are typically designed to meet performance constraints at worst-case conditions, including process corner, temperature, IR-drop, and neighboring net switching pattern…