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20072024
most citedBRDS: An FPGA-based LSTM Accelerator with Row-Balanced Dual-Ratio Sparsification

8 citations · 10 across the 7 of their papers we have counts for

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cs.AR2024

On the Impact of ISA Extension on Energy Consumption of I-Cache in Extensible Processors

Noushin Behboudi, Mehdi Kamal, Ali Afzali-Kusha

As is widely known, the computational speed and power consumption are two critical parameters in microprocessor design. A solution for these issues is the application specific inst…

cs.AR2022

AMR-MUL: An Approximate Maximally Redundant Signed Digit Multiplier

Saba Amanollahi, Mehdi Kamal, Ali-Afzali-Kusha +1

In this paper, we present an energy-efficient, yet high-speed approximate maximally redundant signed digit (MRSD) multiplier (called AMR-MUL) based on a parallel structure. For the…

cs.AR2022

Heterogeneous Multi-core Array-based DNN Accelerator

Mohammad Ali Maleki, Mehdi Kamal, Ali Afzali-Kusha

In this article, we investigate the impact of architectural parameters of array-based DNN accelerators on accelerator's energy consumption and performance in a wide variety of netw…

cs.AR2021★ 8 cited

BRDS: An FPGA-based LSTM Accelerator with Row-Balanced Dual-Ratio Sparsification

Seyed Abolfazl Ghasemzadeh, Erfan Bank Tavakoli, Mehdi Kamal +2

In this paper, first, a hardware-friendly pruning algorithm for reducing energy consumption and improving the speed of Long Short-Term Memory (LSTM) neural network accelerators is…

cs.AR2007

Simultaneous Reduction of Dynamic and Static Power in Scan Structures

Shervin Sharifi, Javid Jaffari, Mohammad Hosseinabady +2

Power dissipation during test is a major challenge in testing integrated circuits. Dynamic power has been the dominant part of power dissipation in CMOS circuits, however, in futur…