8 citations · 10 across the 7 of their papers we have counts for
7 papers
On the Impact of ISA Extension on Energy Consumption of I-Cache in Extensible Processors
Noushin Behboudi, Mehdi Kamal, Ali Afzali-Kusha
As is widely known, the computational speed and power consumption are two critical parameters in microprocessor design. A solution for these issues is the application specific inst…
AMR-MUL: An Approximate Maximally Redundant Signed Digit Multiplier
Saba Amanollahi, Mehdi Kamal, Ali-Afzali-Kusha +1
In this paper, we present an energy-efficient, yet high-speed approximate maximally redundant signed digit (MRSD) multiplier (called AMR-MUL) based on a parallel structure. For the…
Heterogeneous Multi-core Array-based DNN Accelerator
Mohammad Ali Maleki, Mehdi Kamal, Ali Afzali-Kusha
In this article, we investigate the impact of architectural parameters of array-based DNN accelerators on accelerator's energy consumption and performance in a wide variety of netw…
BRDS: An FPGA-based LSTM Accelerator with Row-Balanced Dual-Ratio Sparsification
Seyed Abolfazl Ghasemzadeh, Erfan Bank Tavakoli, Mehdi Kamal +2
In this paper, first, a hardware-friendly pruning algorithm for reducing energy consumption and improving the speed of Long Short-Term Memory (LSTM) neural network accelerators is…
A2P-MANN: Adaptive Attention Inference Hops Pruned Memory-Augmented Neural Networks
Mohsen Ahmadzadeh, Mehdi Kamal, Ali Afzali-Kusha +1
In this work, to limit the number of required attention inference hops in memory-augmented neural networks, we propose an online adaptive approach called A2P-MANN. By exploiting a…
Space Expansion of Feature Selection for Designing more Accurate Error Predictors
Shayan Tabatabaei Nikkhah, Mehdi Kamal, Ali Afzali-Kusha +1
Approximate computing is being considered as a promising design paradigm to overcome the energy and performance challenges in computationally demanding applications. If the case wh…
Simultaneous Reduction of Dynamic and Static Power in Scan Structures
Shervin Sharifi, Javid Jaffari, Mohammad Hosseinabady +2
Power dissipation during test is a major challenge in testing integrated circuits. Dynamic power has been the dominant part of power dissipation in CMOS circuits, however, in futur…