TA-LRW: A Replacement Policy for Error Rate Reduction in STT-MRAM Caches

Elham Cheshmikhani, Hamed Farbeh, Seyed Ghassem Miremadi +1

As technology process node scales down, on-chip SRAM caches lose their efficiency because of their low scalability, high leakage power, and increasing rate of soft errors. Among em…