2 papers
cs.AR2022
TA-LRW: A Replacement Policy for Error Rate Reduction in STT-MRAM Caches
Elham Cheshmikhani, Hamed Farbeh, Seyed Ghassem Miremadi +1
As technology process node scales down, on-chip SRAM caches lose their efficiency because of their low scalability, high leakage power, and increasing rate of soft errors. Among em…
cs.ET2019
3DCAM: A Low Overhead Crosstalk Avoidance Mechanism for TSV-Based 3D ICs
Reza Mirosanlou, Mohammadkazem Taram, Zahra Shirmohammadi +1
Three Dimensional Integrated Circuits (3D IC) offer lower power consumption, higher performance, higher bandwidth, and scalability over the conventional two dimensional ICs. Throug…