11 citations · 31 across the 19 of their papers we have counts for
8 papers · 1 filter
Harvesting AI Computation at the Edge via Generic Approximation
Yihan Wang, Huiru Yan, Luxin Zhang +6
With the widespread adoption of AI in various IoT scenarios such as smart sensing and processing, AI chips have become a common component at the edge. These chips are typically spe…
LUT-DLA: Lookup Table as Efficient Extreme Low-Bit Deep Learning Accelerator
Guoyu Li, Shengyu Ye, Chunyun Chen +6
The emergence of neural network capabilities invariably leads to a significant surge in computational demands due to expanding model sizes and increased computational complexity. T…
Cross-Layer Optimization for Fault-Tolerant Deep Learning
Qing Zhang, Cheng Liu, Bo Liu +4
Fault-tolerant deep learning accelerator is the basis for highly reliable deep learning processing and critical to deploy deep learning in safety-critical applications such as avio…
DeepBurning-MixQ: An Open Source Mixed-Precision Neural Network Accelerator Design Framework for FPGAs
Erjing Luo, Haitong Huang, Cheng Liu +5
Mixed-precision neural networks (MPNNs) that enable the use of just enough data width for a deep learning task promise significant advantages of both inference accuracy and computi…
Fault-Tolerant Deep Learning: A Hierarchical Perspective
Cheng Liu, Zhen Gao, Siting Liu +3
With the rapid advancements of deep learning in the past decade, it can be foreseen that deep learning will be continuously deployed in more and more safety-critical applications s…
Taming Process Variations in CNFET for Efficient Last Level Cache Design
Dawen Xu, Zhuangyu Feng, Cheng Liu +5
Carbon nanotube field-effect transistors (CNFET) emerge as a promising alternative to CMOS transistors for the much higher speed and energy efficiency, which makes the technology p…
R2F: A Remote Retraining Framework for AIoT Processors with Computing Errors
Dawen Xu, Meng He, Cheng Liu +5
AIoT processors fabricated with newer technology nodes suffer rising soft errors due to the shrinking transistor sizes and lower power supply. Soft errors on the AIoT processors pa…
HyCA: A Hybrid Computing Architecture for Fault Tolerant Deep Learning
Cheng Liu, Cheng Chu, Dawen Xu +5
Hardware faults on the regular 2-D computing array of a typical deep learning accelerator (DLA) can lead to dramatic prediction accuracy loss. Prior redundancy design approaches ty…