7 citations · 18 across the 11 of their papers we have counts for
8 papers · 1 filter
David vs. Goliath: Can Small Models Win Big with Agentic AI in Hardware Design?
Shashwat Shankar, Subhranshu Pandey, Innocent Dengkhw Mochahari +4
Large Language Model(LLM) inference demands massive compute and energy, making domain-specific tasks expensive and unsustainable. As foundation models keep scaling, we ask: Is bigg…
Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTS
Matthew DeLorenzo, Animesh Basak Chowdhury, Vasudev Gohil +4
Existing large language models (LLMs) for register transfer level code generation face challenges like compilation failures and suboptimal power, performance, and area (PPA) effici…
Retrieval-Guided Reinforcement Learning for Boolean Circuit Minimization
Animesh Basak Chowdhury, Marco Romanelli, Benjamin Tan +2
Logic synthesis, a pivotal stage in chip design, entails optimizing chip specifications encoded in hardware description languages like Verilog into highly efficient implementations…
Towards the Imagenets of ML4EDA
Animesh Basak Chowdhury, Shailja Thakur, Hammond Pearce +2
Despite the growing interest in ML-guided EDA tools from RTL to GDSII, there are no standard datasets or prototypical learning tasks defined for the EDA problem domain. Experience…
INVICTUS: Optimizing Boolean Logic Circuit Synthesis via Synergistic Learning and Search
Animesh Basak Chowdhury, Marco Romanelli, Benjamin Tan +2
Logic synthesis is the first and most vital step in chip design. This steps converts a chip specification written in a hardware description language (such as Verilog) into an optim…
Too Big to Fail? Active Few-Shot Learning Guided Logic Synthesis
Animesh Basak Chowdhury, Benjamin Tan, Ryan Carey +3
Generating sub-optimal synthesis transformation sequences ("synthesis recipe") is an important problem in logic synthesis. Manually crafted synthesis recipes have poor quality. Sta…