activity
20192026
most citedDSPatch: Dual Spatial Pattern Prefetcher

75 citations · 79 across the 8 of their papers we have counts for

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13 papers · 1 filter

cs.AR2026

Valinor: Architectural Support for Fast, Energy-Efficient and Programmable Physical Memory Allocation

Konstantinos Kanellopoulos, Spiros Galanopoulos, Konstantinos Sgouras +7

Physical memory allocation establishes virtual-to-physical mappings on demand. In current systems, each minor page fault traps into the kernel and triggers pipeline flushes, stalls…

cs.AR2026

Machine Learning-Driven Intelligent Memory System Design: From On-Chip Caches to Storage

Rahul Bera, Rakesh Nadig, Onur Mutlu

Despite the data-rich environment in which memory systems of modern computing platforms operate, many state-of-the-art architectural policies employed in the memory system rely on…

cs.AR2026

Mitigating the Memory Bottleneck with Machine Learning-Driven and Data-Aware Microarchitectural Techniques

Rahul Bera

Modern applications process massive data volumes that overwhelm the storage and retrieval capabilities of memory systems, making memory the primary performance and energy-efficienc…

cs.AR2026

Conduit: Programmer-Transparent Near-Data Processing Using Multiple Compute-Capable Resources in Solid State Drives

Rakesh Nadig, Vamanan Arulchelvan, Mayank Kabra +9

Solid-state drives (SSDs) are well suited for near-data processing (NDP) because they: (1) store large application datasets, and (2) support three NDP paradigms: in-storage process…

cs.AR20261 cited

Athena: Synergizing Data Prefetching and Off-Chip Prediction via Online Reinforcement Learning

Rahul Bera, Zhenrong Lang, Caroline Hengartner +4

Prefetching and off-chip prediction are two techniques proposed to hide long memory access latencies in high-performance processors. In this work, we demonstrate that: (1) prefetch…

cs.AR2025

Revelator: Rapid Data Fetching via System-Software-Guided Hash-based Speculative Address Translation

Konstantinos Kanellopoulos, Konstantinos Sgouras, Harsh Songara +7

Address translation is a major performance bottleneck in modern computing systems. Predicting the physical address (PA) of requested data before address translation completes can h…