94 citations · 219 across the 18 of their papers we have counts for
21 papers
Trail: Scalable and Low-Cost Temporal TLB Prefetching via Page-Table-Embedded Deltas
Konstantinos Kanellopoulos, Konstantinos Sgouras, Harsh Songara +2
Address translation is a major bottleneck in data-intensive workloads. TLB prefetching can hide translation latency, but existing spatial prefetchers struggle with irregular access…
Valinor: Architectural Support for Fast, Energy-Efficient and Programmable Physical Memory Allocation
Konstantinos Kanellopoulos, Spiros Galanopoulos, Konstantinos Sgouras +7
Physical memory allocation establishes virtual-to-physical mappings on demand. In current systems, each minor page fault traps into the kernel and triggers pipeline flushes, stalls…
Machine Learning-Driven Intelligent Memory System Design: From On-Chip Caches to Storage
Rahul Bera, Rakesh Nadig, Onur Mutlu
Despite the data-rich environment in which memory systems of modern computing platforms operate, many state-of-the-art architectural policies employed in the memory system rely on…
Mitigating the Memory Bottleneck with Machine Learning-Driven and Data-Aware Microarchitectural Techniques
Rahul Bera
Modern applications process massive data volumes that overwhelm the storage and retrieval capabilities of memory systems, making memory the primary performance and energy-efficienc…
Conduit: Programmer-Transparent Near-Data Processing Using Multiple Compute-Capable Resources in Solid State Drives
Rakesh Nadig, Vamanan Arulchelvan, Mayank Kabra +9
Solid-state drives (SSDs) are well suited for near-data processing (NDP) because they: (1) store large application datasets, and (2) support three NDP paradigms: in-storage process…
Athena: Synergizing Data Prefetching and Off-Chip Prediction via Online Reinforcement Learning
Rahul Bera, Zhenrong Lang, Caroline Hengartner +4
Prefetching and off-chip prediction are two techniques proposed to hide long memory access latencies in high-performance processors. In this work, we demonstrate that: (1) prefetch…
Revelator: Rapid Data Fetching via System-Software-Guided Hash-based Speculative Address Translation
Konstantinos Kanellopoulos, Konstantinos Sgouras, Harsh Songara +7
Address translation is a major performance bottleneck in modern computing systems. Predicting the physical address (PA) of requested data before address translation completes can h…
CIPHERMATCH: Accelerating Homomorphic Encryption-Based String Matching via Memory-Efficient Data Packing and In-Flash Processing
Mayank Kabra, Rakesh Nadig, Harshita Gupta +7
Homomorphic encryption (HE) allows secure computation on encrypted data without revealing the original data, providing significant benefits for privacy-sensitive applications. Many…
Harmonia: Enhancing Data Placement and Migration in Hybrid Storage Systems via Multi-Agent Reinforcement Learning
Rakesh Nadig, Vamanan Arulchelvan, Rahul Bera +7
Modern high-performance computing (HPC) environments rely on hybrid storage systems (HSS) that combine multiple storage devices with diverse latency, bandwidth, endurance, and capa…
Constable: Improving Performance and Power Efficiency by Safely Eliminating Load Instruction Execution
Rahul Bera, Adithya Ranganathan, Joydeep Rakshit +8
Load instructions often limit instruction-level parallelism (ILP) in modern processors due to data and resource dependences they cause. Prior techniques like Load Value Prediction…
Virtuoso: Enabling Fast and Accurate Virtual Memory Research via an Imitation-based Operating System Simulation Methodology
Konstantinos Kanellopoulos, Konstantinos Sgouras, F. Nisa Bostanci +7
The unprecedented growth in data demand from emerging applications has turned virtual memory (VM) into a major performance bottleneck. Researchers explore new hardware/OS co-design…
Victima: Drastically Increasing Address Translation Reach by Leveraging Underutilized Cache Resources
Konstantinos Kanellopoulos, Hong Chul Nam, F. Nisa Bostanci +5
Address translation is a performance bottleneck in data-intensive workloads due to large datasets and irregular access patterns that lead to frequent high-latency page table walks…
Utopia: Fast and Efficient Address Translation via Hybrid Restrictive & Flexible Virtual-to-Physical Address Mappings
Konstantinos Kanellopoulos, Rahul Bera, Kosta Stojiljkovic +8
Conventional virtual memory (VM) frameworks enable a virtual address to flexibly map to any physical address. This flexibility necessitates large data structures to store virtual-t…
Hermes: Accelerating Long-Latency Load Requests via Perceptron-Based Off-Chip Load Prediction
Rahul Bera, Konstantinos Kanellopoulos, Shankar Balachandran +4
Long-latency load requests continue to limit the performance of high-performance processors. To increase the latency tolerance of a processor, architects have primarily relied on t…
Sectored DRAM: A Practical Energy-Efficient and High-Performance Fine-Grained DRAM Architecture
Ataberk Olgun, F. Nisa Bostanci, Geraldo F. Oliveira +6
We propose Sectored DRAM, a new, low-overhead DRAM substrate that reduces wasted energy by enabling fine-grained DRAM data transfers and DRAM row activation. Sectored DRAM leverage…
Sibyl: Adaptive and Extensible Data Placement in Hybrid Storage Systems Using Online Reinforcement Learning
Gagandeep Singh, Rakesh Nadig, Jisung Park +7
Hybrid storage systems (HSS) use multiple different storage devices to provide high and scalable storage capacity at high performance. Recent research proposes various techniques t…
Casper: Accelerating Stencil Computation using Near-cache Processing
Alain Denzler, Rahul Bera, Nastaran Hajinazar +4
Stencil computation is one of the most used kernels in a wide variety of scientific applications, ranging from large-scale weather prediction to solving partial differential equati…
Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning
Rahul Bera, Konstantinos Kanellopoulos, Anant V. Nori +3
Past research has proposed numerous hardware prefetching techniques, most of which rely on exploiting one specific type of program context information (e.g., program counter, cache…
BurstLink: Techniques for Energy-Efficient Conventional and Virtual Reality Video Display
Jawad Haj-Yahya, Jisung Park, Rahul Bera +5
Conventional planar video streaming is the most popular application in mobile systems and the rapid growth of 360 video content and virtual reality (VR) devices are accelerating th…
Proximu$: Efficiently Scaling DNN Inference in Multi-core CPUs through Near-Cache Compute
Anant V. Nori, Rahul Bera, Shankar Balachandran +5
Deep Neural Network (DNN) inference is emerging as the fundamental bedrock for a multitude of utilities and services. CPUs continue to scale up their raw compute capabilities for D…
DSPatch: Dual Spatial Pattern Prefetcher
Rahul Bera, Anant V. Nori, Onur Mutlu +1
High main memory latency continues to limit performance of modern high-performance out-of-order cores. While DRAM latency has remained nearly the same over many generations, DRAM b…