activity
20162024
most citedExploiting Errors for Efficiency: A Survey from Circuits to Algorithms

15 citations · 32 across the 7 of their papers we have counts for

collaborators

7 papers

cs.CL2024★ 1 cited

Cost-Efficient Large Language Model Serving for Multi-turn Conversations with CachedAttention

Bin Gao, Zhuomin He, Puru Sharma +6

Interacting with humans through multi-turn conversations is a fundamental feature of large language models (LLMs). However, existing LLM serving engines executing multi-turn conver…

cs.OS2024

numaPTE: Managing Page-Tables and TLBs on NUMA Systems

Bin Gao, Qingxuan Kang, Hao-Wei Tee +3

Memory management operations that modify page-tables, typically performed during memory allocation/deallocation, are infamous for their poor performance in highly threaded applicat…

cs.ET2022★ 4 cited

Efficiently Enabling Block Semantics and Data Updates in DNA Storage

Puru Sharma, Cheng-Kai Lim, Dehui Lin +2

We propose a novel and flexible DNA-storage architecture, which divides the storage space into fixed-size units (blocks) that can be independently and efficiently accessed at rando…

cs.ET2022★ 10 cited

Managing Reliability Skew in DNA Storage

Dehui Lin, Yasamin Tabatabaee, Yash Pote +1

DNA is emerging as an increasingly attractive medium for data storage due to a number of important and unique advantages it offers, most notably the unprecedented durability and de…

cs.AR2020★ 1 cited

SPARTA: A Divide and Conquer Approach to Address Translation for Accelerators

Javier Picorel, Seyed Alireza Sanaee Kohroudi, Zi Yan +3

Virtual memory (VM) is critical to the usability and programmability of hardware accelerators. Unfortunately, implementing accelerator VM efficiently is challenging because the are…

cs.AR2018★ 15 cited

Exploiting Errors for Efficiency: A Survey from Circuits to Algorithms

Phillip Stanley-Marbell, Armin Alaghi, Michael Carbin +13

When a computational task tolerates a relaxation of its specification or when an algorithm tolerates the effects of noise in its execution, hardware, programming languages, and sys…

cs.AR2016★ 1 cited

Near-Memory Address Translation

Javier Picorel, Djordje Jevdjic, Babak Falsafi

Memory and logic integration on the same chip is becoming increasingly cost effective, creating the opportunity to offload data-intensive functionality to processing units placed i…