317 citations · 849 across the 20 of their papers we have counts for
22 papers
Influence of Radiation and AC Coupling on Time Performance of Analog Pixels Test Structures in 65 nm CMOS technology
Gianluca Aglieri Rinella, Luca Aglietta, Matias Antonelli +44
Monolithic Active Pixel Sensors (MAPS) in advanced CMOS imaging technologies are key to next-generation tracking systems for high-energy physics, where radiation hardness and preci…
Sensor operating point calibration and monitoring of the ALICE Inner Tracking System during LHC Run 3
D. Agguiaro, G. Aglieri Rinella, L. Aglietta +285
The new Inner Tracking System (ITS2) of the ALICE experiment began operation in 2021 with the start of LHC Run 3. Compared to its predecessor, ITS2 offers substantial improvements…
Characterisation of the first wafer-scale prototype for the ALICE ITS3 upgrade: the monolithic stitched sensor (MOSS)
Omar Abdelrahman, Gianluca Aglieri Rinella, Luca Aglietta +136
This paper presents the characterisation and testing of the first wafer-scale monolithic stitched sensor (MOSS) prototype developed for the ALICE ITS3 upgrade that is to be install…
Further Characterisation of Digital Pixel Test Structures Implemented in a 65 nm CMOS Process
Gianluca Aglieri Rinella, Nicole Apadula, Anton Andronic +55
The next generation of MAPS for future tracking detectors will have to meet stringent requirements placed on them. One such detector is the ALICE ITS3 that aims to be very light at…
Time performance of Analog Pixel Test Structures with in-chip operational amplifier implemented in 65 nm CMOS imaging process
Gianluca Aglieri Rinella, Luca Aglietta, Matias Antonelli +43
In the context of the CERN EP R&D on monolithic sensors and the ALICE ITS3 upgrade, the Tower Partners Semiconductor Co (TPSCo) 65 nm process has been qualified for use in high ene…
Characterisation of analogue Monolithic Active Pixel Sensor test structures implemented in a 65 nm CMOS imaging process
Gianluca Aglieri Rinella, Giacomo Alocco, Matias Antonelli +91
Analogue test structures were fabricated using the Tower Partners Semiconductor Co. CMOS 65 nm ISC process. The purpose was to characterise and qualify this process and to optimise…