6 papers · 1 filter
Fine Grain 3D Integration for Microarchitecture Design Through Cube Packing Exploration
Yongxiang Liu, Yuchun Ma, Eren Kurshan +2
Most previous 3D IC research focused on stacking traditional 2D silicon layers, so the interconnect reduction is limited to inter-block delays. In this paper, we propose techniques…
TopSort: A High-Performance Two-Phase Sorting Accelerator Optimized on HBM-based FPGAs
Weikang Qiao, Licheng Guo, Zhenman Fang +2
The emergence of high-bandwidth memory (HBM) brings new opportunities to boost the performance of sorting acceleration on FPGAs, which was conventionally bounded by the available o…
TENET: A Framework for Modeling Tensor Dataflow Based on Relation-centric Notation
Liqiang Lu, Naiqing Guan, Yuyue Wang +5
Accelerating tensor applications on spatial architectures provides high performance and energy-efficiency, but requires accurate performance models for evaluating various dataflow…
When HLS Meets FPGA HBM: Benchmarking and Bandwidth Optimization
Young-kyu Choi, Yuze Chi, Jie Wang +2
With the recent release of High Bandwidth Memory (HBM) based FPGA boards, developers can now exploit unprecedented external memory bandwidth. This allows more memory-bounded applic…
Rapid Cycle-Accurate Simulator for High-Level Synthesis
Yuze Chi, Young-kyu Choi, Jason Cong +1
A large semantic gap between the high-level synthesis (HLS) design and the low-level (on-board or RTL) simulation environment often creates a barrier for those who are not FPGA exp…
Best-Effort FPGA Programming: A Few Steps Can Go a Long Way
Jason Cong, Zhenman Fang, Yuchen Hao +4
FPGA-based heterogeneous architectures provide programmers with the ability to customize their hardware accelerators for flexible acceleration of many workloads. Nonetheless, such…