23 citations · 76 across the 10 of their papers we have counts for
3 papers · 1 filter
AKER: A Design and Verification Framework for Safe andSecure SoC Access Control
Francesco Restuccia, Andres Meza, Ryan Kastner
Modern systems on a chip (SoCs) utilize heterogeneous architectures where multiple IP cores have concurrent access to on-chip shared resources. In security-critical applications, I…
Isadora: Automated Information Flow Property Generation for Hardware Designs
Calvin Deutschbein, Andres Meza, Francesco Restuccia +2
Isadora is a methodology for creating information flow specifications of hardware designs. The methodology combines information flow tracking and specification mining to produce a…
Hardware-efficient Residual Networks for FPGAs
Olivia Weng, Alireza Khodamoradi, Ryan Kastner
Residual networks (ResNets) employ skip connections in their networks -- reusing activations from previous layers -- to improve training convergence, but these skip connections cre…