23 citations · 76 across the 10 of their papers we have counts for
10 papers
Information Flow Coverage Metrics for Hardware Security Verification
Andres Meza, Ryan Kastner
Security graphs model attacks, defenses, mitigations, and vulnerabilities on computer networks and systems. With proper attributes, they provide security metrics using standard gra…
Open-source FPGA-ML codesign for the MLPerf Tiny Benchmark
Hendrik Borras, Giuseppe Di Guglielmo, Javier Duarte +15
We present our development experience and recent results for the MLPerf Tiny Inference Benchmark on field-programmable gate array (FPGA) platforms. We use the open-source hls4ml an…
AKER: A Design and Verification Framework for Safe andSecure SoC Access Control
Francesco Restuccia, Andres Meza, Ryan Kastner
Modern systems on a chip (SoCs) utilize heterogeneous architectures where multiple IP cores have concurrent access to on-chip shared resources. In security-critical applications, I…
Isadora: Automated Information Flow Property Generation for Hardware Designs
Calvin Deutschbein, Andres Meza, Francesco Restuccia +2
Isadora is a methodology for creating information flow specifications of hardware designs. The methodology combines information flow tracking and specification mining to produce a…
Hardware-efficient Residual Networks for FPGAs
Olivia Weng, Alireza Khodamoradi, Ryan Kastner
Residual networks (ResNets) employ skip connections in their networks -- reusing activations from previous layers -- to improve training convergence, but these skip connections cre…
A Unified Model for Gate Level Propagation Analysis
Jeremy Blackstone, Wei Hu, Alric Althoff +3
Classic hardware verification techniques (e.g., X-propagation and fault-propagation) and more recent hardware security verification techniques based on information flow tracking (I…