67 citations · 95 across the 5 of their papers we have counts for
6 papers
TurboFuzz: FPGA Accelerated Hardware Fuzzing for Processor Agile Verification
Yang Zhong, Haoran Wu, Xueqi Li +4
Verification is a critical process for ensuring the correctness of modern processors. The increasing complexity of processor designs and the emergence of new instruction set archit…
fSEAD: a Composable FPGA-based Streaming Ensemble Anomaly Detection Library
Binglei Lou, David Boland, Philip H. W. Leong
Machine learning ensembles combine multiple base models to produce a more accurate output. They can be applied to a range of machine learning problems, including anomaly detection.…
LUXOR: An FPGA Logic Cell Architecture for Efficient Compressor Tree Implementations
SeyedRamin Rasoulinezhad, Siddhartha, Hao Zhou +3
We propose two tiers of modifications to FPGA logic cell architecture to deliver a variety of performance and utilization benefits with only minor area overheads. In the irst tier,…
MajorityNets: BNNs Utilising Approximate Popcount for Improved Efficiency
Seyedramin Rasoulinezhad, Sean Fox, Hao Zhou +3
Binarized neural networks (BNNs) have shown exciting potential for utilising neural networks in embedded implementations where area, energy and latency constraints are paramount. W…
AddNet: Deep Neural Networks Using FPGA-Optimized Multipliers
Julian Faraone, Martin Kumm, Martin Hardieck +4
Low-precision arithmetic operations to accelerate deep-learning applications on field-programmable gate arrays (FPGAs) have been studied extensively, because they offer the potenti…
Unrolling Ternary Neural Networks
Stephen Tridgell, Martin Kumm, Martin Hardieck +4
The computational complexity of neural networks for large scale or real-time applications necessitates hardware acceleration. Most approaches assume that the network architecture a…