67 citations · 74 across the 2 of their papers we have counts for
4 papers
LUXOR: An FPGA Logic Cell Architecture for Efficient Compressor Tree Implementations
SeyedRamin Rasoulinezhad, Siddhartha, Hao Zhou +3
We propose two tiers of modifications to FPGA logic cell architecture to deliver a variety of performance and utilization benefits with only minor area overheads. In the irst tier,…
MajorityNets: BNNs Utilising Approximate Popcount for Improved Efficiency
Seyedramin Rasoulinezhad, Sean Fox, Hao Zhou +3
Binarized neural networks (BNNs) have shown exciting potential for utilising neural networks in embedded implementations where area, energy and latency constraints are paramount. W…
AddNet: Deep Neural Networks Using FPGA-Optimized Multipliers
Julian Faraone, Martin Kumm, Martin Hardieck +4
Low-precision arithmetic operations to accelerate deep-learning applications on field-programmable gate arrays (FPGAs) have been studied extensively, because they offer the potenti…
Unrolling Ternary Neural Networks
Stephen Tridgell, Martin Kumm, Martin Hardieck +4
The computational complexity of neural networks for large scale or real-time applications necessitates hardware acceleration. Most approaches assume that the network architecture a…